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參數(shù)資料
| 型號(hào)： | TLV5610IYZ |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, BGA20 |
| 封裝： | GREEN, WCSP-20 |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 180K |
| 代理商： | TLV5610IYZ |
www.ti.com
SERIAL CLOCK FREQUENCY AND UPDATE RATE
f
sclkmax +
1
t
whmin )
t
wlmin
+ 30MHz
(2)
f
updatemax +
1
16 t
whmin )
t
wlmin
+ 1.95MHz
(3)
DATA FORMAT
REGISTER MAP
SBAS389A – JULY 2006 – REVISED JULY 2006
APPLICATION INFORMATION (continued)
The maximum serial clock frequency is given by:
The maximum update rate is given by:
Note that the maximum update rate is just a theoretical value for the serial interface because the settling time of
the DAC must also be considered.
The 16 bit data word consists of two parts:
1. Address bits (D15...D12)
2. Data bits (D11...D0)
Table 1. Data Format(1)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
A0
Data
(1)
Ax: Address bits. See Table 2.
Table 2. Register Map
A3
A2
A1
A0
FUNCTION
0
DAC A
0
1
DAC B
0
1
0
DAC C
0
1
DAC D
0
1
0
DAC E
0
1
0
1
DAC F
0
1
0
DAC G
0
1
DAC H
1
0
CTRL0
1
0
1
CTRL1
1
0
1
0
Preset
1
0
1
Reserved
1
0
DAC A and B
1
0
1
DAC C and D
1
0
DAC E and F
1
DAC G and H
9
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