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參數(shù)資料
| 型號： | TLV5610IYZ |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, BGA20 |
| 封裝： | GREEN, WCSP-20 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 180K |
| 代理商： | TLV5610IYZ |
www.ti.com
ELECTRICAL CHARACTERISTICS
SBAS389A – JULY 2006 – REVISED JULY 2006
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply
Fast
16
21
mA
No load, VREF = 4.096V, all inputs = DVDD or
IDD
Power-supply current
GND
Slow
6
8
mA
Power-down supply current
0.1
A
POR
Power-on threshold
2
V
PSRR
Power-supply rejection ratio
Full-scale; see Note (1)
–60
dB
Static DAC Specifications
Resolution
12
Bits
INL
Integral nonlinearity
Code 40 to 4095, VREF = 2V, 4V
±2
±6
LSB
DNL
Differential nonlinearity
Code 40 to 4095, VREF = 2V, 4V
±0.5
±1
LSB
EZS
Zero-scale error (offset error at zero-scale)
±30
mV
EZS TC
Zero-scale error temperature coefficient
30
V/°C
EG
Gain error
±0.6
% Full-Scale V
EG TC
Gain error temperature coefficient
10
ppm/
°C
Output Specifications
VO
Voltage output range
RL = 10k
0
AVDD – 4
V
Output load regulation accuracy
RL = 2k vs 10k
±0.3
% Full-Scale V
Reference Input
VI
Input voltage range
0
AVDD
V
RI
Input resistance
100
k
CI
Input capacitance
5
pF
Fast
2.2
MHz
Reference input bandwidth
VREF = 0.4VPP + 2.048VDC, input code = 0x800
Slow
1.9
MHz
Reference feedthrough
VREF = 2VPP at 1kHz + 2.048VDC(2)
–84
dB
Digital Inputs
IIH
High-level digital input current
VI = DVDD
1
A
IIL
Low-level digital input current
VI = 0V
–1
A
CI
Input capacitance
8
pF
Digital Outputs
VOH
High-level digital output voltage
RL = 10k
2.6
V
VOL
Low-level digital output voltage
RL = 10k
0.4
V
Output voltage rise time
RL = 10k, CL = 20pF, incl. propagation delay
7
20
ns
Analog Output Dynamic Performance
Fast
1
3
s
tS(FS)
Output settling time(3), full-scale
RL = 10k, CL = 1000pF
Slow
3
7
s
Fast
0.5
1
s
tS(CC)
Output settling time(4), code to code
RL = 10k, CL = 1000pF
Slow
1
2
s
Fast
4
10
V/
s
SR
Slew rate(5)
RL = 10k, CL = 1000pF
Slow
1
3
V/
s
Glitch energy
See Note (6)
4
nV-s
Channel crosstalk
10kHz sine, 4VPP
–90
dB
(1)
Power-supply rejection ratio at full-scale is measured by varying AVDD and is given by the following equation:
PSRR = 20 log[(EG(AVDDmax) – EG(AVDDmin))]/VDDmax.
(2)
Reference feedthrough is measured at the DAC output with an input code = 0x000.
(3)
Settling time is the time for the output signal to remain within
±0.5 LSB of the final measured value for a digital input code change of
0x80 to 0xFFF and 0xFFF to 0x080, respectively. Assured by design; not production tested.
(4)
Settling time is the time for the output signal to remain within
±0.5 LSB of the final measured value for a digital input code change of one
count. The max time applies to code changes near zero scale or full-scale. Assured by design; not production tested.
(5)
Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
(6)
Code transition: 0x7FF to 0x800.
3
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