參數(shù)資料
型號(hào)： TLV5613CPW
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 12-BIT DAC, PDSO20
封裝： PLASTIC, TSSOP-20
文件頁(yè)數(shù)： 18/23頁(yè)
文件大?。?/td> 447K
代理商： TLV5613CPW
TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)
power supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD =5V
Fast
1.6
3
mA
IDD
Power supply current
No load,
All inputs = GND or DVDD
VDD = 5 V
Slow
0.5
1.3
mA
IDD
Power supply current
All inputs = GND or DVDD,
DAC latch = 0x800
VDD =3V
Fast
1.4
2.7
mA
VDD = 3 V
Slow
0.4
1.1
mA
Power down supply current
See Figure 14
0.01
10
A
PSRR
Power supply rejection ratio
Zero scale,
See Note 2
–65
dB
PSRR
Power supply rejection ratio
Full scale,
See Note 3
–65
dB
NOTES:
2. Power supply rejection ratio at zero scale is measured by varying AVDD and is given by:
PSRR = 20 log [(EZS(AVDDmax) – EZS(AVDDmin))/AVDDmax]
3. Power supply rejection ratio at full scale is measured by varying AVDD and is given by:
PSRR = 20 log [(EG(AVDDmax) – EG(AVDDmin))/AVDDmax]
static DAC specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
Vref(REFIN) = 2.048 V, 1.024 V
12
bits
Integral nonlinearity (INL), end point adjusted
Vref(REFIN) = 2.048 V, 1.024 V,
See Note 4
±1.5
±4
LSB
Differential nonlinearity (DNL)
Vref(REFIN) = 2.048 V, 1.024 V,
See Note 5
±0.4
± 1
LSB
EZS
Zero-scale error (offset error at zero scale)
Vref(REFIN) = 2.048 V, 1.024 V,
See Note 6
±3
±20
mV
Zero-scale-error temperature coefficient
Vref(REFIN) = 2.048 V, 1.024 V,
See Note 7
3
ppm/
°C
EG
Gain error
Vref(REFIN) = 2.048 V, 1.024 V,
See Note 8
±0.25
±0.5
% of FS
voltage
Gain error temperature coefficient
Vref(REFIN) = 2.048 V, 1.024 V,
See Note 9
1
ppm/
°C
NOTES:
4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax – Tmin).
8. Gain error is the deviation from the ideal output (Vref – 1 LSB) with an output load of 10 k excluding the effects of the zero-error.
9. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin).
output specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO
Output voltage
RL = 10 k
0
AVDD–0.4
V
Output load regulation accuracy
VO(OUT) = 4.096 V,
RL = 2 k,
0.1
0.29
% of FS
voltage
IOSC(source) Output short circuit source current
VO(OUT) =0V input all 1s
AVDD = 5 V
–100
mA
IOSC(source) Out ut short circuit source current
VO(OUT) = 0 V, in ut all 1s
AVDD = 3 V
–25
mA
IOSC(sink)
Output short circuit sink current
RL = 100 input all 1s
AVDD = 5 V
–10
mA
IOSC(sink)
Out ut short circuit sink current
RL = 100 , in ut all 1s
AVDD = 3 V
–10
mA
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