參數(shù)資料
型號： TLV5613CPW
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 12-BIT DAC, PDSO20
封裝： PLASTIC, TSSOP-20
文件頁數(shù)： 19/23頁
文件大?。?/td> 447K
代理商： TLV5613CPW
TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)
reference input (REFIN)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Vref
Input voltage reference
See Note 10
0
AVDD– 1.5
V
Ri
Input resistance
10
M
Ci
Input capacitance
5
pF
Reference input bandwidth
REF=0 2Vpp +1 024Vdc
Fast mode
1.6
MHz
Reference in ut bandwidth
REF = 0.2 Vpp + 1.024 V dc
Slow mode
1
MHz
Reference feed through
REF = 1 Vpp at 1 kHz + 1.024 V dc,
See Note 10
–60
dB
NOTES: 10. Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH
High-level digital input current
VI = DVDD
1
A
IIL
Low-level digital input current
VI = 0 V
–1
A
Ci
Input capacitance
8
pF
operating characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t (FS)
Output settling time full scale
RL = 10 k,
See Note 11
Fast
1
3
s
ts(FS)
Output settling time, full scale
L
,
CL = 100 pF,
Slow
3.5
7
s
t (CC)
Output settling time code to code
RL = 10 k,
See Note 12
Fast
0.5
1.5
s
ts(CC)
Output settling time, code-to-code
L
,
CL = 100 pF,
Slow
1
2
s
SR
Slew rate
RL = 10 k,
See Note 13
Fast
8
V/
s
SR
Slew rate
L
,
CL = 100 pF,
Slow
1.5
V/
s
Glitch energy
Code-to-code transition
1
nV–s
S/N
Signal-to-noise
65
78
S/(N+D)
Signal-to-noise + distortion
fs = 480 KSPS, fout = 1 kHz,
58
69
dB
THD
Total harmonic distortion
s
,
out
,
RL = 10 k,
CL = 100 pF
–68
–60
dB
Spurious free dynamic range
60
72
NOTES: 11. Settling time is the time for the output signal to remain within
±0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0x3FF or 0x3FF to 0x020.
12. Settling time is the time for the output signal to remain within
± 0.5 LSB of the final measured value for a digital input code change
of one count. The max time applies to code changes near zero scale or full scale.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
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