參數(shù)資料
型號： TLV5614CDR
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 9 us SETTLING TIME, 12-BIT DAC, PDSO16
封裝： GREEN, PLASTIC, MS-012AC, SOIC-16
文件頁數(shù)： 30/34頁
文件大?。?/td> 737K
代理商： TLV5614CDR
TLV5614
2.7-V TO 5.5-V 12-BIT 3-
S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)
individual DAC output specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO
Voltage output range
RL = 10 k
0
AVDD–0.4
V
Output load regulation accuracy
RL = 2 k vs 10 k
0.1
0.25
% of FS
voltage
reference inputs (REFINAB, REFINCD)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
Input voltage range
See Note 10
0
AVDD–1.5
V
RI
Input resistance
10
M
CI
Input capacitance
5
pF
Reference feed through
REFIN = 1 Vpp at 1 kHz + 1.024 V dc
(see Note 11)
–75
dB
Reference input bandwidth
REFIN
0 2 V
1 024 V dc large signal
Slow
0.5
MHz
Reference input bandwidth
REFIN = 0.2 Vpp + 1.024 V dc large signal
Fast
1
MHz
NOTES: 10. Reference input voltages greater than VDD/2 cause output saturation for large DAC codes.
11. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref (REFINAB or REFINCD)
input = 1.024 Vdc + 1 Vpp at 1 kHz.
digital inputs (DIN, CS, LDAC, PD)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH
High-level digital input current
VI = VDD
±1
A
IIL
Low-level digital input current
VI = 0 V
±1
A
CI
Input capacitance
3
pF
power supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5-V supply,
No load Clock running
Slow
1.6
2.4
mA
I
Power supply current
No load, Clock running,
All inputs 0 V or VDD
Fast
3.8
5.6
mA
IDD
Power supply current
3-V supply,
No load Clock running
Slow
1.2
1.8
mA
No load, Clock running,
All inputs 0 V or DVDD
Fast
3.2
4.8
mA
Power down supply current (see Figure 12)
10
nA
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