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參數(shù)資料
| 型號(hào)： | TLV5614CDR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 9 us SETTLING TIME, 12-BIT DAC, PDSO16 |
| 封裝： | GREEN, PLASTIC, MS-012AC, SOIC-16 |
| 文件頁數(shù)： | 32/34頁 |
| 文件大小： | 737K |
| 代理商： | TLV5614CDR |
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TLV5614
2.7-V TO 5.5-V 12-BIT 3-
S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)
digital input timing requirements
MIN
NOM
MAX
UNIT
tsu(CS–FS)
Setup time, CS low before FS
↓
10
ns
tsu(FS–CK)
Setup time, FS low before first negative SCLK edge
8
ns
tsu(C16–FS)
Setup time, sixteenth negative SCLK edge after FS low on which bit D0 is sampled before
rising edge of FS
10
ns
tsu(C16–CS)
Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS
is used instead of the SCLK positive edge to update the DAC, then the setup time is between
the FS rising edge and CS rising edge.
10
ns
twH
Pulse duration, SCLK high
25
ns
twL
Pulse duration, SCLK low
25
ns
tsu(D)
Setup time, data ready before SCLK falling edge
8
ns
th(D)
Hold time, data held valid after SCLK falling edge
5
ns
twH(FS)
Pulse duration, FS high
20
ns
PARAMETER MEASUREMENT INFORMATION
12
3
4
5
15
16
D15
D14
D13
D12
D1
D0
tsu(FS-CK)
tsu(CS-FS)
twH(FS)
th(D)
tsu(D)
twH
twL
tsu(C16-CS)
tsu(C16-FS)
SCLK
DIN
CS
FS
Figure 1. Timing Diagram
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| TLV5614CPWR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit 3 us Quad DAC Serial Input RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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