參數(shù)資料
型號(hào)： TLV5626IDG4
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： DAC
英文描述： SERIAL INPUT LOADING, 2.8 us SETTLING TIME, 8-BIT DAC, PDSO8
封裝： PLASTIC, SOIC-8
文件頁(yè)數(shù)： 14/19頁(yè)
文件大?。?/td> 424K
代理商： TLV5626IDG4
TLV5626
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
power supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 5 V,
Fast
4.2
7
mA
DD
Int. ref.
Slow
2
3.6
mA
VDD = 3 V,
Fast
3.7
6.3
mA
IDD
Power supply current
No load,
All inputs = AGND or VDD
DD
Int. ref.
Slow
1.7
3.0
mA
IDD
Power supply current
All inputs = AGND or VDD,
DAC latch = 0x800
VDD = 5 V,
Fast
3.8
6.3
mA
DD
Ext. ref.
Slow
1.7
3.0
mA
VDD = 3 V,
Fast
3.4
5.7
mA
DD
Ext. ref.
Slow
1.4
2.6
mA
Power-down supply current
1
A
PSRR
Power supply rejection ratio
Zero scale, See Note 2
–65
dB
PSRR
Power supply rejection ratio
Full scale,
See Note 3
–65
dB
NOTES:
2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:
PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax]
3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax]
static DAC specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
8
bits
INL
Integral nonlinearity, end point adjusted
See Note 4
±0.4
±1
LSB
DNL
Differential nonlinearity
See Note 5
±0.1
±0.5
LSB
EZS
Zero-scale error (offset error at zero scale)
See Note 6
±24
mV
EZS TC
Zero-scale-error temperature coefficient
See Note 7
10
ppm/
°C
EG
Gain error
See Note 8
±0.6
% full
scale V
EG TC
Gain error temperature coefficient
See Note 9
10
ppm/
°C
NOTES:
4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax – Tmin).
8. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 k excluding the effects of the zero-error.
9. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin).
output specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO
Output voltage
RL = 10 k
0
VDD–0.4
V
Output load regulation accuracy
VO = 4.096 V, 2.048 V,
RL = 2 k vs 10 k
±0.25
% full
scale V
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