參數(shù)資料
型號： TLV5626IDG4
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 2.8 us SETTLING TIME, 8-BIT DAC, PDSO8
封裝： PLASTIC, SOIC-8
文件頁數(shù)： 16/19頁
文件大?。?/td> 424K
代理商： TLV5626IDG4
TLV5626
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS236A –JUNE 1999 – REVISED JUNE 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
digital input timing requirements
MIN
NOM
MAX
UNIT
tsu(CS–CK)
Setup time, CS low before first negative SCLK edge
10
ns
tsu(C16-CS)
Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge
10
ns
twH
SCLK pulse width high
25
ns
twL
SCLK pulse width low
25
ns
tsu(D)
Setup time, data ready before SCLK falling edge
10
ns
th(D)
Hold time, data held valid after SCLK falling edge
5
ns
PARAMETER MEASUREMENT INFORMATION
twL
SCLK
CS
DIN
D15
D14
D13
D12
D1
D0
X
1
X
2
3
4
5 15
16
X
twH
tsu(D) th(D)
tsu(CS-CK)
tsu(C16-CS)
Figure 1. Timing Diagram
相關(guān)PDF資料
PDF描述
TLV5626CDRG4 SERIAL INPUT LOADING, 2.8 us SETTLING TIME, 8-BIT DAC, PDSO8
TLV5626CDR SERIAL INPUT LOADING, 2.8 us SETTLING TIME, 8-BIT DAC, PDSO8
TLV5627CD SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 8-BIT DAC, PDSO16
TLV5627CPW SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 8-BIT DAC, PDSO16
TLV5627CDR SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 8-BIT DAC, PDSO16
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