參數(shù)資料
型號： TLV5628INE4
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： OCTAL, SERIAL INPUT LOADING, 10 us SETTLING TIME, 8-BIT DAC, PDIP16
封裝： ROHS COMPLIANT, PLASTIC, DIP-16
文件頁數(shù)： 14/18頁
文件大?。?/td> 410K
代理商： TLV5628INE4
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
data interface (continued)
Table 2 lists the A2, A1, and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applied reference voltage and GND.
Table 1. Ideal Output Transfer
D7
D6
D5
D4
D3
D2
D1
D0
OUTPUT VOLTAGE
0
GND
0
0000001
(1/256)
× REF (1+RNG)
0
1111111
(127/256)
× REF (1+RNG)
1
0000000
(128/256)
× REF (1+RNG)
1
(255/256)
× REF (1+RNG)
Table 2. Serial Input Decode
A2
A1
A0
DAC UPDATED
0
DACA
0
1
DACB
0
1
0
DACC
0
1
DACD
1
0
DACE
1
0
1
DACF
1
0
DACG
1
DACH
相關(guān)PDF資料
PDF描述
TLV5628IN OCTAL, SERIAL INPUT LOADING, 10 us SETTLING TIME, 8-BIT DAC, PDIP16
TLV5628IDWG4 OCTAL, SERIAL INPUT LOADING, 10 us SETTLING TIME, 8-BIT DAC, PDSO16
TLV5628CDWR OCTAL, SERIAL INPUT LOADING, 10 us SETTLING TIME, 8-BIT DAC, PDSO16
TLV5628CN OCTAL, SERIAL INPUT LOADING, 10 us SETTLING TIME, 8-BIT DAC, PDIP16
TLV5628IDWRG4 OCTAL, SERIAL INPUT LOADING, 10 us SETTLING TIME, 8-BIT DAC, PDSO16
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