參數(shù)資料
型號(hào)： TLV5628INE4
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： OCTAL, SERIAL INPUT LOADING, 10 us SETTLING TIME, 8-BIT DAC, PDIP16
封裝： ROHS COMPLIANT, PLASTIC, DIP-16
文件頁(yè)數(shù)： 16/18頁(yè)
文件大?。?/td> 410K
代理商： TLV5628INE4
TLV5628C, TLV5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS108A – JANUARY 1995 – REVISED NOVEMBER 1995
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD – GND)
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range, VID
GND – 0.3 V to VDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range
GND – 0.3 V to VDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLV5628C
0
°C to 70°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLV5628I
– 40
°C to 85°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg
–50
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
230
°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VDD
2.7
3.3
5.25
V
High-level digital input voltage, VIH
0.8 VDD
V
Low-level digital input voltage, VIL
0.8
V
Reference voltage, Vref [A|B|C|D|E|F|G|H], X1 gain
VDD– 1.5
V
Load resistance, RL
10
k
Setup time, data input, tsu(DATA-CLK) (see Figures 1 and 2)
50
ns
Valid time, data input valid after CLK
↓, tv(DATA-CLK) (see Figures 1 and 2)
50
ns
Setup time, CLK eleventh falling edge to LOAD, tsu(CLK-LOAD) (see Figure 1)
50
ns
Setup time, LOAD
↑ to CLK↓, tsu(LOAD-CLK) (see Figure 1)
50
ns
Pulse duration, LOAD, tw(LOAD) (see Figure 1)
250
ns
Pulse duration, LDAC, tw(LDAC) (see Figure 2)
250
ns
Setup time, LOAD
↑ to LDAC↓, tsu(LOAD-LDAC) (see Figure 2)
0
ns
CLK frequency
1
MHz
Operating free air temperature TA
TLV5628C
0
70
°C
Operating free-air temperature, TA
TLV5628I
–40
85
°C
相關(guān)PDF資料
PDF描述
TLV5628IN OCTAL, SERIAL INPUT LOADING, 10 us SETTLING TIME, 8-BIT DAC, PDIP16
TLV5628IDWG4 OCTAL, SERIAL INPUT LOADING, 10 us SETTLING TIME, 8-BIT DAC, PDSO16
TLV5628CDWR OCTAL, SERIAL INPUT LOADING, 10 us SETTLING TIME, 8-BIT DAC, PDSO16
TLV5628CN OCTAL, SERIAL INPUT LOADING, 10 us SETTLING TIME, 8-BIT DAC, PDIP16
TLV5628IDWRG4 OCTAL, SERIAL INPUT LOADING, 10 us SETTLING TIME, 8-BIT DAC, PDSO16
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