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參數(shù)資料
| 型號： | TLV977-10CPFB |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 4/21頁 |
| 文件大?。?/td> | 289K |
| 代理商： | TLV977-10CPFB |
TLV977-10
3-V, 10-BIT, 21 MSPS, AREA CCD SENSOR PROCESSOR
SLAS229 – AUGUST 1999
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
REGISTER DEFINITION
optical black calibration register format
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TB9
TB8
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
Default test register value = 0110000000
test register description
BIT
NAME
DESCRIPTION
D9 – D6
TB9 – TB6
These four bits are used to program the internal dc bias current. The bias current programming uses following
equation:
Ibias = 8 A + (code) × 2 A
Hence, Ibias varies from 8 A (code=0000) to 38 A (code=1111), with a linear step of 2 A.
Recommend to set the code to 0101.
D5, D4
TB5, TB4
Test outputs (pin 34/35 – TPM/TPP) control:
TB5
TB4
0
0 or 1
High impedance outputs at pin TPP and TPM.
1
0
Inverted internal CDS clock at pin TPP.
Inverted internal PGA clock at pin TPM.
1
PGA noninverting output at pin TPP.
PGA inverting output at pin TPM.
D3
TB3
1 – use external reference, power down internal reference
0 – use internal reference (default).
D2
TB2
Reserved
D1, D0
TB1, TB0
Test output (pin 23 – DACT) control for offset DACs:
TB1
TB0
0
0 or 1
High impedance outputs at pin DACT (default = 00)
1
0
DACT = fine offset DAC output at pin DACT
1
DACT = coarse offset DAC output at pin DACT
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