參數(shù)資料
型號(hào)： TLV977-10CPFB
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP48
封裝： PLASTIC, TQFP-48
文件頁(yè)數(shù)： 7/21頁(yè)
文件大小： 289K
代理商： TLV977-10CPFB
TLV977-10
3-V, 10-BIT, 21 MSPS, AREA CCD SENSOR PROCESSOR
SLAS229 – AUGUST 1999
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
voltage references
An internal precision voltage reference of 1.5 V nominal is provided. This reference voltage is used to generate
the ADC Ref– voltage of 1 V and Ref+ of 2 V. It also sets the clamp voltage. All internally-generated voltages
are fixed values and cannot be adjusted.
power supply
The TLV977-10 has several power supply pins. Each major internal analog block has a dedicated AVDD supply
terminal. All internal digital circuitry is powered by the DVDD. Both AVDD and DVDD are 3 V nominal.
The DIVDD and DIGND pins supply power to the output digital driver (D9–D0). The DIVDD is independent of
the DVDD and can be operated from 1.8 V to 4.4 V. This allows the outputs to interface with digital ASICs
requiring different supply voltages.
grounding and decoupling
General practices apply to the PCB design to limit high frequency transients and noise that are fed back into
the supply and reference lines. This requires that the supply and reference terminals be sufficiently bypassed.
In the case of power supply decoupling. A 0.1
F ceramic chip capacitor are adequate to keep the impedance
low over a wide frequency range. Recommended external decoupling for the three voltage reference terminals
is shown in Figure 3. Since their effectiveness depends largely on the proximity to the individual supply terminal,
all decoupling capacitors should be placed as close to the supply terminals as possible.
To reduce high-frequency and noise-coupling, it is highly recommended that digital and analog ground be
shorted immediately outside the package. This can be accomplished by running a low impedance line between
the DGND and AGND, under the package.
automatic optical black and offset correction
In the TLV977-10, the optical black and system channel offset corrections are performed by an auto digital
feadback loop. Two DACs are used to compensate for both channel offset and the optical black offset. A coarse
correction DAC (CDAC) is located before PGA gain stage and a fine correction DAC (FDAC) is located after
the gain stage. The digital calibration system is capable of correcting the optical black and channel offset down
to one ADC LSB accuracy.
The TLV977-10 automatically starts the auto-calibration whenever the OBCLP input is pulled low, the OBCLP
pulse should be wide enough to cover one positive half cycle of the ADCCLK as shown in Figure 1.
For each line, the optical black pixels plus the channel offset are sampled and converted to digital data by the
ADC. A digital circuit averages the data during the optical black pixels. The final averaged result is compared
digitally with the desired output code stored in the Vb register (default is 40H); then control logic adjusts the
FDAC to make the ADC output equal to the Vb. If the offset is out of the range of the FDAC (
±255 ADC LSBs),
the error is corrected by both CDAC and FDAC. The CDAC increments or decrements by one CDAC LSB
depending on whether the offset is negative of positive, until the output is within the range of the FDAC. The
remaining residue is corrected by the FDAC.
The relationship among the FDAC, CDAC, and ADC in terms of number of ADC LSBs is as follows,
1 FDAC LSB = 1 ADC LSB,
1 CDAC LSB = 0.5 x PGA linear gain
× 1 ADC LSB.
For example, if PGA gain = 2 (6 dB), then, 1 CDAC LSB = 1 ADC LSBs.
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