參數(shù)資料
型號(hào)： TMC2302AH5C1
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： Image Manipulation Sequencer
中文描述： 16-BIT, DSP-ADDRESS SEQUENCER, PPGA120
封裝： CAVITY-UP, PLASTIC, PGA-120
文件頁(yè)數(shù)： 18/36頁(yè)
文件大?。?/td> 188K
代理商： TMC2302AH5C1
TMC2302A
PRODUCT SPECIFICATION
18
P
Switching Characteristics
Note:
1. All transitions are measured at a 1.5V level except for t
DIS
and T
EMA
.
Timing Diagrams
Figure 4a. Timing Diagram,
Pixel Clock, Control, and Outputs
Figure 4b. Timing Diagram, Preload Parameters
Parameter
t
DO
t
HO
t
ENA
t
DIS
-1
Test Conditions
V
DD
= Min, C
LOAD
= 25pF
V
DD
= Max, C
LOAD
= 25pF
V
DD
= Min, C
LOAD
= 25pF
V
DD
= Min, C
LOAD
= 25pF
Min.
Max.
15
Min.
Max. Units
12
Output Delay
Output Hold Time
Three-State Output Enable Delay
1
Three-State Output Disable Delay
1
ns
ns
ns
ns
4
4
12
15
12
15
CLK
INPUTS1
OUTPUTS2
tCY
tS
tH
tD
tHO
VALID
65-2302-11
VALID
tPWL
tPWH
Notes:
1. Except OES, OET, and OEK.
2. Assumes OES, OET, and OEK = LOW. All pipeline latency
parameters set to 0.
DAT 1
ADR 1
IWR
IDAT
IADR
ICS
tS
tH
tPWL
65-2302-12
Value "DAT 1" is loaded into address "ADR 1" on the second
rising edge of IWR, since ICS = 0, having been acquired by the
input register on the first edge.
Applications Discussion
The Image Transformation Polynomial
On any given clock cycle, when performing a two-dimen-
sional geometric transformation the addresses output by the
row (X/U) TMC2302A are generated by forward difference
accumulation according to the following third-order polyno-
mial:
x(u,v) = a + bu + cu
2
+du
3
+ ev + fvu + gvu
2
+ hvu
3
+ iv
2
+ jv
2
u + kv
2
u
2
+ Iv
2
u
3
+ mv
3
+ nv
3
u + ov
3
u
2
+ pv
3
u
3
+ FOV CAX(ca)
The polynomial utilized for three-dimensional transforms is:
x(u,v,w) = a + bu + ev + kw + fuv + ivw + luw + juvw
+ FOV CAX (ca)
where 0
￡
u
￡
UMAX-UMIN, 0
￡
v
￡
VMAX-VMIN,
0
￡
w
￡
WMAX-WMIN, and the polynomials for the column
or page devices are obtained by replacing the x by a y or z, as
appropriate.
相關(guān)PDF資料
PDF描述
TMC2302AKEC Image Manipulation Sequencer
TMC2302AKEC1 Image Manipulation Sequencer
TMC2330AH5C Coordinate Transformer 16 x 16 Bit, 40 MOPS
TMC2330AH5C1 Coordinate Transformer 16 x 16 Bit, 40 MOPS
TMC2330A Coordinate Transformer 16 x 16 Bit, 40 MOPS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMC2302AKEC 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer
TMC2302AKEC1 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer
TMC2330A 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS
TMC2330AG1C 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS
TMC2330AG1C1 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS
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