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參數(shù)資料
| 型號： | TMC2302AH5C1 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理外設 |
| 英文描述： | Image Manipulation Sequencer |
| 中文描述： | 16-BIT, DSP-ADDRESS SEQUENCER, PPGA120 |
| 封裝： | CAVITY-UP, PLASTIC, PGA-120 |
| 文件頁數(shù)： | 7/36頁 |
| 文件大?。?/td> | 188K |
| 代理商： | TMC2302AH5C1 |
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PRODUCT SPECIFICATION
TMC2302A
7
P
Clocks
CLK
J12
70
System Clock .
internal registers except the control parameter preload registers.
All timing specifications except those are referenced to the rising
edge of CLK.
Input Parameter Write Clock.
The internal image transformation
and configuration control parameter registers are double buffered
to simplify interfacing with system controllers. Depending on the
state of the chip selects ICS, control words input to IDAT
the corresponding addresses presented to IADR
into the outer preload registers on the rising edge of the Input
parameter Write clock IWR. The last parameter must be loaded
twice on two consecutive rising edges of IWR.
The pixel clock of the TMC2302A strobes all
IWR
J13
71
15-0
and
6-0
are strobed
Inputs
IDAT
15-0
A10, C9,
B10, A11,
B11, C10,
A12, B12,
B13, C13,
D12, D13,
E12, E13,
F13, G13
A7, C7, B7,
A8, B8, C8,
A9
99, 98, 97,
96, 95, 94,
93, 92, 87,
86, 85, 83,
82, 81, 78,
77
Input Parameter Data.
parameter Input Data are presented, along with the appropriate
input register address word IADR
port, and are latched into the preload registers on the next rising
edge of IWR. Preload register updates are disabled by the chip
select control ICS. See Figure 3.
Configuration and transformation
6-0
, to the parameter Input Data
IADR
6-0
107, 106,
105, 104,
103, 102,
101
Input Parameter Address.
currently indicated by the Input parameter register Address
IADR
6-0
is loaded with the data presented to input port IDAT on the
rising edge of IWR, as demonstrated in Figure 3.
The input parameter preload register
Outputs
SADR
23-0
B6, C6, A5,
B5, C5, B4,
A3, A2, B2,
B1, C1, D2,
D1, E2, E1,
F2, F1, G1.
H1, H2, J1,
J2, K1, K2
109, 110,
111, 112,
114, 115,
116, 117, 2,
3, 6, 7, 9,
10, 11, 13,
14, 17, 18,
19, 21, 22,
23, 25
32, 34, 35,
36, 38, 39,
40, 41
Source Address.
the source image pixel value currently being resampled is output
through the Source Address port SADR
forced to the high-impedance state by the enable control OES.
The 24-bit address of one dimension (X, Y, Z) of
23-0
. This port can be
KADR
7-0
N2, M3, N3,
M4, N4, M5,
N5, L6
Coefficient Address.
dimension of the spiral interpolation walk performed by the
TMC2302A, as determined by the transform parameter KERNEL,
are generated by the internal walk counter and output at the
Coefficient Address output port KADR
to the high-impedance state by the enable control OEK.
The integer address steps for each
7-0
. This port can be forced
Pin Descriptions
(continued)
Pin Name
Pin Number
PPGA
Pin Function Description
MQFP
相關PDF資料 |
PDF描述 |
|---|---|
| TMC2302AKEC | Image Manipulation Sequencer |
| TMC2302AKEC1 | Image Manipulation Sequencer |
| TMC2330AH5C | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AH5C1 | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330A | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2302AKEC | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AKEC1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2330A | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C1 | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
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