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參數(shù)資料
| 型號： | TMC2302AKEC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理外設 |
| 英文描述： | Image Manipulation Sequencer |
| 中文描述： | 16-BIT, DSP-ADDRESS SEQUENCER, PQFP120 |
| 封裝： | METRIC, QFP-120 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 188K |
| 代理商： | TMC2302AKEC |
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PRODUCT SPECIFICATION
TMC2302A
11
P
Transformation Coefficient and
Configuration and Control
Parameters
The TMC2302A is intended to act as a co-processor, requir-
ing only that the user program the device to perform the
image transformation desired by loading in the appropriate
device configuration and transformation control parameters
discussed in this section. The user then issues an “Init”
command, allowing his system to run unattended until the
completion of the image when a “Done” flag is generated to
inform the host system.
The capabilities and flexibility of the TMC2302A Image
Manipulation Sequencer are apparent when reviewing the
following tables which define the transformation coefficient
and configuration and control parameters. These tables are
broken up into two separate groups. The first parameters dis-
cussed are the control words which select the dimension cal-
culated, the functional configuration of each device, the
working space in which they will operate, the size of the
interpolation kernel desired, and the timing of the various
address and control signals involved in handling the pixel
data pipeline. The second parameters are the polynomial
transform coefficients used in performing image manipula-
tion. The TMC2302A utilizes three levels of internal 48-bit
accumulators to calculate these values by forward difference
accumulation, generating no significant cumulative spatial
error for most applications. The user must be aware that all
internal parameter and coefficient registers must be set by
the user, including resetting after powerup any unused con-
trol words or coefficients.
As mentioned above, the TMC2302A also features user-
programmable image data pipeline configuration controls.
All output signals except the source and coefficient address
outputs can be individually delayed by the user up to seven
clocks after the nominal system timing illustrated in Table 4.
This allows the user to software-configure the TMC2302As
in his system to match his pixel interpolator, image buffer,
and interpolation coefficient RAM structure timing.
The user can also program the device to continue into the
next image for a set number of clock cycles after the Done
flag has appeared. First, this “flushes” the final resampled
pixel data word through the interpolation pipeline, all the
way to the target image RAM. Also, valid pixel data will
then appear on the first clock of the next transform indepen-
dent of the length of the pixel pipeline, incurring no lost
clock cycles.
Device Configuration and Control
Parameters
Note:
The parameter UMAX must exceed UMIN so as to
ensure that a minimum of 5 system clock cycles in two-
dimensional operation, or 15 clock cycles in three-dimen-
sional operation, pass between the periods in which these
two target address values are generated. Thus in 2D nearest
neighbor operation UMAX must be 5 greater than UMIN. In
2D bilinear interpolation mode (4-pixel two-dimensional
kernel) the distance must be two pixels in the target image
(actually enforcing a spacing of 8 system clocks).
UMIN,
VMIN,
WMIN
The memory addresses of the target image
boundaries corresponding to the top, left side,
and front page of the new image being gener-
ated are defined in all devices of the user's
system by the parameters UMIN, VMIN, and
WMIN, respectively. At the beginning of the
transformation, the initial source image coor-
dinate (X
0
, Y
0
, Z
0
) will be mapped to this
coordinate set. The numeric format assumed
is 12-bit unsigned binary integer.
UMAX,
VMAX,
WMAX
The memory addresses of the target image
boundaries corresponding to the bottom,
right side, and last page of the image being
generated are defined in all devices by the
parameters UMAX, VMAX, and WMAX,
respectively. These values should be greater
than the UMIN/VMIN/WMIN values defined
above. Numeric format assumed is unsigned
12-bit binary integer.
UMINI,
VMINI,
WMINI
The target image addresses corresponding to
those of the top, left side, and front page of the
2 or 3 dimensional region indicated by the
valid target address flag TVAL are UMINI,
VMINI, and WMINI, respectively. Thus, to
define a valid region beginning at “m,” the
MINI parameter value is “m,” These parame-
ters are assumed to be in 12-bit unsigned
binary integer format. Proper TVAL operation
requires UMIN < UMINI < UMAXI
< UMAX, etc.
UMAXI,
VMAXI,
WMAXI
The target image addresses one more than
those of the right side, bottom and back page
of the region indicated by the valid target
address flag TVAL are UMAXI, VMAXI, and
WMAXI, respectively. Thus, to define a valid
region ending at “n,” the MAXI parameter
value is “n+1”. These parameters are assumed
to be in 12-bit unsigned integer format.
相關PDF資料 |
PDF描述 |
|---|---|
| TMC2302AKEC1 | Image Manipulation Sequencer |
| TMC2330AH5C | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AH5C1 | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330A | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2302AKEC1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2330A | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C1 | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AH5C | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
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