- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384014 > TMC2302AKEC (FAIRCHILD SEMICONDUCTOR CORP) Image Manipulation Sequencer PDF資料下載
參數(shù)資料
| 型號： | TMC2302AKEC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Image Manipulation Sequencer |
| 中文描述： | 16-BIT, DSP-ADDRESS SEQUENCER, PQFP120 |
| 封裝： | METRIC, QFP-120 |
| 文件頁數(shù)： | 15/36頁 |
| 文件大?。?/td> | 188K |
| 代理商： | TMC2302AKEC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
PRODUCT SPECIFICATION
TMC2302A
15
P
Figure 3. Image transformation and configuration control parameters register structure
Figure 3 depicts the control preload register structure and
Figure 4B gives the corresponding timing relationships.
Table 4. Nominal Output Signal Timing
SADR
23-0
1
X
I-1,J,0
X
I-1,J,1
X
I-1,J,2
X
I-1,J,K
X
I,J,0
X
I,J,1
X
I,J,2
X
I,J,K
Note:
1. KADR
7-0
timing identical.
ACC
0
1
1
TADR
11-0
U
L-1,M
U
L-1,M
U
L-1,M
TWR
1
1
1
END
0
0
0
DONE
0
0
0
1
0
1
1
U
L-1,M
U
L,M
U
L,M
U
L,M
0
1
1
1
1
1
1
1
0
0
0
0
1
U
L,M
0
1
1
68
(a) Internal logic. Registers are enabled for the start of
each new transition or by INIT HIGH.
16
TMC2302A
TO
REST
OF
CHIP
INTERNAL
REGISTER
PRELOAD
REGISTER
DE-
CODE
7
PIXEL
CLOCK
IDAT
15-0
65-2302-07
IWR
ICS
CLK
INIT
SYNC
IADR
6-0
EN
EN
(a)
The nominal sequence of address and control signals of a
two-dimensional, single-pass-programmed TMC2302A
system, with all PIPE parameters set to 0, is shown in
Table 4. Here, the values of the last two new target image
pixels U
L-l,M
and U
L,M
are being calculated, and the begin-
ning and end of the interpolation walks of length K which
sample source image pixels in the neighborhod of locations
(X
I-1,J
, X
I,J
) can be seen. Utilizing the arrival of the source
image address (SADR
31-0
) as a reference point, the other
signals shown can be delayed up to seven clock cycles from
the nominal timing shown here, allowing the user to config-
ure these outputs to match the timing latencies of his pixel
data path structure. Considerable speed and timing variations
in image buffer memory, data register, and pixel interpolator
structure can thus be accomodated, with minimal corre-
sponding support hardware. Also see “PFLS,” in the Device
Configuration and Control Parameters section.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMC2302AKEC1 | Image Manipulation Sequencer |
| TMC2330AH5C | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AH5C1 | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330A | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2302AKEC1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2330A | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C1 | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AH5C | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。