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參數資料
| 型號： | TMC2376 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | PC-to-TV Video Standards Converter(PC到TV視頻標準變換器) |
| 中文描述： | PC到電視視頻標準轉換器（電腦到電視視頻標準變換器） |
| 文件頁數： | 17/48頁 |
| 文件大?。?/td> | 233K |
| 代理商： | TMC2376 |
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TMC2376
PRODUCT SPECIFICATION
17
P
Functional Description
Figure 1. Functional Block Diagram
V
T
V
TOUT
Capture
Timing and
Control
ADCK
PLL
Clamp
RGB/YC
B
C
R
Matrix
Gain
YC
B
C
/RGB
Matrix
Video
Encoder
Horizontal
Scaller
Read
Timing
and
Control
Read Pixel
Buffer
BPF
Encoder and
Timing Control
FSK PLL
M
FLP_RST
8-bit
A/D
8-bit
A/D
8-bit
A/D
9-bit
D/A
9-bit
D/A
9-bit
D/A
Frame Store
Controller
C
A
1
R
W
F
F
D
C
D
1
R
R
V
R
C
B
R
G
B
Y/R/V
Comp
Y
C
YUV
C
Y
CKNTSC
CKPAL
XTALNTSC
XTALPAL
CSYNC
CVBS/G/Y
C/B/U
RGB
ADXCK
ADXCKSEL\
ADCK/N
CLAMP
R
7-0
G
7-0
B
7-0
XA/D_SEL\
HS
VS
2366-03
Vertical
Scaler
Flicker
Filter
Write Pixel
Buffer
Write Timing
and Control
Voltage
Follower
BiPGen
Serial Bus
Interface
S
S
0
S
S
+
Notch
Filter
FSCK_OUT
Details of how to connect and setup the TMC2376 are
included in this section. Overall design principles are in the
Architectural Overview section. Operation of the TMC2376
is divided into four sections:
Capture Engine
Frame Store Controller
Encoder Engine
Serial Control Port
Capture Engine
A/D Converters, Bit Pattern Generator, RGB/YUV Matrix,
Vertical Scaler and Flicker Filter comprise the Capture
Engine.
Timing and Control
Timing of the Capture Engine is derived from the Input Con-
trol Block which contains a series of counters and decoders
synchronized to the A/D sample clock, ADCK. ADCK is
derived from a phase locked loop referenced to the leading
edge of horizontal sync.
Sync polarity is auto-detected by sensing the leading edge of
horizontal sync HS and vertical sync, VS. This edge is the
reference for the phase-locked loop tracking the horizontal
pixel count and the vertical line counter.
Registers that interface with the Capture Timing and Control
block are:
IHS
IHC (read only)
IVC (read only)
Capture Control also coordinates hand off of data to the
Frame Store Controller.
Input horizontal samples, IHS is the 10-bit terminal count of
the number of pixels per horizontal line between sync pulses.
IHS is the value programmed into the ADCK phase-locked-
loop. If, for example there are to be 800 samples per incom-
ing line, then IHS must be programmed to be 799.
Input horizontal count, IHC is the number of 4f
SC
clock
pulses (14.31818 MHz for NTSC; 17.734 MHz for PAL) that
occur between horizontal sync pulses. This count is stored in
the IHC register that can be read via the serial bus for auto-
matic detection of the format of incoming video.
Input vertical count, IVC is the 10-bit terminal count of the
number of lines that occur between the vertical sync pulses.
This count is stored in the IVC register that can be read via
the serial bus for automatic detection of the format of
incoming video.
Clamps
Incoming RGB video signals must be AC coupled to the A/D
converters. Preceding each A/D converter is an FET clamp
switch which establishes the black reference level of each
video signal by shorting the A/D converter input to ground
when the clamp signal is active. Clamp timing is derived
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