參數(shù)資料
型號： TMC2376
廠商： Fairchild Semiconductor Corporation
英文描述： PC-to-TV Video Standards Converter(PC到TV視頻標(biāo)準(zhǔn)變換器)
中文描述： PC到電視視頻標(biāo)準(zhǔn)轉(zhuǎn)換器（電腦到電視視頻標(biāo)準(zhǔn)變換器）
文件頁數(shù)： 19/48頁
文件大?。?/td> 233K
代理商： TMC2376
TMC2376
PRODUCT SPECIFICATION
19
P
The 512x512 chart is inserted into a 768x768 pixel frame,
displaced 128 pixels from the left boundary and 128 pixels
from the upper boundary. Color bars are each 64 pixels wide.
BIPGEN pixels are clocked at half the rate of internal frame
store clock, FSCK.
Digital RGB Multiplexer
The A/D_SEL pin in conjunction with the BIPGEN bit in the
Command Register controls a triple 24-bit multiplexer that
selects the source of RGB data to be supplied to the digital
gain block. 24-bit RGB data can be accepted from:
TTL compatible RGB input port
A/D converter outputs
BiPGen, the internal test pattern generator
RGB Gain
Following each A/D converter is a digital gain stage that
allows the A/D converter to accommodate either 700 mV or
1000 mV RGB input video signals. Gain is set by the RGB-
GAIN bit of the Mode Register. When using RGBGAIN, VT
must be set to 1000 mV. Consequently, there is a slight loss
in intensity quantization when the peak input level is 700
mV.
RGB/YUV Matrix
Pixels are converted from the 24-bit RGB format to the 24-
bit YUV format by an RGB/YUV matrix. UV data is filtered
and decimated prior to realignment with Y data form a 16-bit
YUV422 data stream.
Command Register bit, UVALT determines the siting of UV
samples relative to Y samples (see Figure 4). In the normal
mode, each U and V sample pair corresponds to an even Y
sample. In the alternating mode, U is sampled on even Y val-
ues and V is sampled on odd Y values. UVALT also impacts
UV reconstruction in the Video Encoder Engine.
Figure 4. Siting of YUV samples determined by UVALT.
Vertical Scaler
16-bit YUV422 data from the Transcoder is passed to the
Vertical Scaler which operates on columns of pixels. Vertical
scale factor is set by programming the VSC registers (regis-
ter numbers E and F). VSC is the Vertical Scale Coefficient,
n which determines the vertical scaling factor:
VSF = (1 - n/64)
n is the reduction (caused by the scaling filter), modulo 64,
in the number incoming vertical lines. With a range: 0
≤
n
≤
32; _
≤
VSF
≤
1.
Line stores used within the scaler are 768 pixels long.
Flicker Filter
Twitter artifacts occurring between odd and even video
fields, can be eliminated by enabling the Flicker Filter. Fil-
tering band-limits the spatial frequencies of columns of pix-
els to remove high frequency components of high/low
luminance boundaries which cause flicker on an interlaced
TV image.
Output of the filter is the weighted average of three consecu-
tive lines incoming lines. Without the flicker filter, one con-
trasting VGA line can be encoded into one field of the TV
video while adjacent lines are encoded onto the other field.
Flicker frequency will be 30 Hz for NTSC and 25 Hz for
PAL. With the flicker filter enabled, there is a slight smearing
of the vertical definition.
Command Register Extended (0x14) bit 0, FLICKON pro-
grams the state of the flicker filter. With FLICKON = 1, 3-
line filtering is activated. With FLICKON = 0, vertical filter-
ing is bypassed.
Line stores used within the flicker filter are 768 pixels long.
Frame Store Controller
Pixel data transfer between the TMC2376 and the Frame
buffer is coordinated by the Frame Store Controller (FSC).
For normal operation, a 16 Mbit SDRAM is connected
between to the frame store controller port. Supported
SDRAM parts include:
Note that the Toshiba part with 64 msec. refresh period is
more suitable for PAL applications using freeze frame and
for 56 Hz incoming vertical refresh. Samsung and NEC parts
have 32 msec. refresh.
Data from the Capture Engine is written into the frame store
in parallel with extraction of data by the encoder engine is
extracted. Read and write buffers at the data port allow data
to be transferred in bursts without interruption of the overall
flow of pixels. Bandwidth of the FSC bus is 80 MHz, suffi-
cient to support maximum rate write cycles from the Capture
Engine simultaneously with full rate Encoder Engine read
cycles.
Pixel data format is YUV422. Bit assignments of consecutive
16-bit data words is shown in Figure 5.
Figure 5. Frame Store Data Bus Format
2366-06
CLK
Y
Y0
Y1
Y2
Y3
UV – NORM
U0
V0
U2
V2
U – ALT
U0
V1
U2
V3
NEC
Samsung
Toshiba
μ
PD451616G5-A10
KM416S1120A-G/F10
TC59S1616AFT-10A
15
C
B7
C
R7
8
7
Y
7
Y
7
0
Y
0
Y
0
C
B6
C
R6
C
B5
C
R5
C
B4
C
R4
C
B3
C
R3
C
B2
C
R2
C
B1
C
R1
C
B0
C
R0
Y
6
Y
6
Y
5
Y
5
Y
4
Y
4
Y
3
Y
3
Y
2
Y
2
Y
1
Y
1
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