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16. Synchronous Serial Interface (SIO2)
16.6 Transfer Mode
TMP86FS64FG
An INTSIO2 interrupt is generated when the specified number of words has been transferred. If the number of
words is to be changed during transfer, the serial interface must be stopped before making the change. The number of
words can be changed during automatic-wait operation of an internal clock. In this case, the serial interface is not
required to be stopped.
Figure 16-6 Number of words to transfer (Example: 1word = 4bit)
16.6 Transfer Mode
SIO2CR1<SIOM> is used to select the transmit, receive, or transmit/receive mode.
16.6.1 4-bit and 8-bit transfer modes
In these modes, firstly set the SIO control register to the transmit mode, and then write first transmit data
(number of transfer words to be transferred) to the data buffer registers (DBR).
After the data are written, the transmission is started by setting SIO2CR1<SIOS> to “1”. The data are then
output sequentially to the SO pin in synchronous with the serial clock, starting with the least significant bit
(LSB). As soon as the LSB has been output, the data are transferred from the data buffer register to the shift
register. When the final data bit has been transferred and the data buffer register is empty, an INTSIO2 (Buffer
empty) interrupt is generated to request the next transmitted data.
When the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next
transmitted data are not loaded to the data buffer register by the time the number of data words specified with
the SIO2CR2<BUF> has been transmitted. Writing even one word of data cancels the automatic-wait; there-
fore, when transmitting two or more words, always write the next word before transmission of the previous
word is completed.
Note:Automatic waits are also canceled by writing to a DBR not being used as a transmit data buffer register; there-
fore, during SIO do not use such DBR for other applications. For example, when 3 words are transmitted, do
not use the DBR of the remained 5 words.
a1
a2
a3
a0
a1
a2
a3
b0
b1
b2
b3
c0
c1
c2
c3
a0
a1
a0
a2
a3
b0
b1
b2
b3
c0
c1
c2
c3
(a) 1 word transmit
(b) 3 words transmit
(c) 3 words receive
SO2 pin
INTSIO2 interrupt
SO2 pin
SI2 pin
SCK2 pin