參數(shù)資料
型號(hào): TMP90PH44
廠商: Toshiba Corporation
英文描述: A System Evaluation LSI With 8-Bit CPU,One-Time PROM(16384 x 8-Bit),RAM(512 x 8-Bit)(系統(tǒng)評(píng)估大規(guī)模集成電路(集成8位CPU,一次可編程ROM(16384 x 8位),RAM(512 x 8位))
中文描述: 一個(gè)系統(tǒng)評(píng)價(jià)芯片與8位CPU,一次性可編程(16384 × 8位),內(nèi)存(512 × 8位)(系統(tǒng)評(píng)估大規(guī)模集成電路(集成8位的CPU,一次可編程ROM更新(16384 x 8位),內(nèi)存(512 × 8位))
文件頁數(shù): 6/20頁
文件大小: 560K
代理商: TMP90PH44
6/20
TOSHIBA CORPORATION
TMP90PH44
Table 2.2 Pin Names and Functions (2/2)
I/O or tristate
(2)
PROM Mode
Pin name
No. of pins
Function
P57
/WR
1
Output
Port 57: A 1-bit output port.
Write: Strobe signal output for writing external memory.
P60 ~ P63
/M00 ~
M03
4
I/0
/Output
Port 6: 4-bit I/O port which allows I/O selection on bit basis.
Stepping motor control port 0 or pattern generation port 0.
P70 ~ P73
/M10 ~
M13
4
I/O
Output
Port 7: 4-bit I/O port which allows I/O selection on bit basis.
Stepping motor control port 0 or pattern generation port 1.
ALE
1
Output
Address latch enable
CLK
1
Output
Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is pulled up internally during resetting.
EA
1
Input
External access: Connects with V
CC
pin in the TMP90PH44 built ROM is used.
RESET
1
Input
Reset: Initializes the TMP90PH44.
(pull-up resistance is built-in).
X1, X2
2
I/O
Crystal oscillator connection pin
VREF
1
Input of reference voltage to A/D converter
AGND
1
GND pin for A/D converter
V
CC
1
Power supply (+5V +/- 10%)
GND
1
GND pin (0V)
Table 2.3
Pin Function
Name
No. of
pins
I/O
Function
Pin Name
(MCU mode)
A7 ~ A0
8
Input
Program Memory Address Input
P73 ~ P70
P63 ~ P60
A13 ~ A8
6
Input
P15 ~ P10
A14
2
Input
Be fixed to “L” level ,
P16
A15
P17
D7 ~ D0
8
I/0
Data Input/Output
P07 ~ P00
OE
1
Input
Output Enable Input
P26
CE
1
Input
Chip Enable Input
P27
VPP
1
Power
Supply
12.5V/5V (Programming Power Supply)
EA
VCC
1
Power Supply
5V
VCC
VSS
1
Power Supply
0V
VSS
Pin Name
No. of pins
I/O
Pin Setting
P20 ~ P27
8
Input
Be fixed to “L” level.
P40 ~ P44
5
Input
Be fixed to “L or H” level.
P45, P46
2
Input
Be fixed to “H” level.
P47
1
Input
Be fixed to “L or H” level.
P50 ~ P53
P30 ~ P37
4
8
Input
Be fixed to “L or H” level.
VREF
1
Be fixed to “L” level.
AGND
1
Be fixed to “L” level.
RESET
1
Input
Be fixed to “L” level.
CLK
1
Input
Be fixed to “L” level.
ALE
1
Output
Open
X1
1
Input
Resonator connection pin
X2
1
Output
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