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| 型號(hào)： | TMP91FW60FG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-44 |
| 文件頁(yè)數(shù)： | 254/322頁(yè) |
| 文件大小： | 4595K |
| 代理商： | TMP91FW60FG |
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Page 33
2007-10-15
TMP91FW60
3.2
Micro DMA Processing
In addition to general-purpose interrupt processing, the TMP91FW60 supports a micro DMA function. Interrupt
requests set by micro DMA perform micro DMA processing at the highest priority level (Level 6) among maskable
interrupts, regardless of the priority level of the particular interrupt source. The micro DMA has 4 channels and is
possible continuous transmission by specifying the described later burst mode.
The micro DMA has 4 channels and is possible continuous transmission by specifying the described later burst
mode.
Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU goes
to a standby mode (STOP, IDLE1 and IDLE2) by HALT instruction, the requirement of micro DMA will be ignored
(Pending) and DMA transfer is started after release HALT.
3.2.1
Micro DMA Operation
When an interrupt request specified by the micro DMA start vector register is generated, the micro DMA
triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request in spite
of any interrupt source’s level. The micro DMA is ignored on <IFF2:0> = “7”.
The 4 micro DMA channels allow micro DMA processing to be set for up to 4 types of interrupts at any one
time. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared.
The data are automatically transferred once (1/2/4 bytes) from the transfer source address to the transfer des-
tination address set in the control register, and the transfer counter is decreased by 1 (
1). If the decreased
result is “0”, the micro DMA transfer end interrupt (INTTC0 to INTTC3) passes from the CPU to the interrupt
controller. In addition, the micro DMA start vector register DMAnV is cleared to 0, the next micro DMA is
disabled and micro DMA processing completes. If the decreased result is other than “0”, the micro DMA pro-
cessing completes if it does not specify the described later burst mode. In this case, the micro DMA transfer
end interrupt (INTTC0 to INTTC3) aren’t generated.
If an interrupt request is triggered for the interrupt source in use during the interval between the clearing of
the micro DMA start vector and the next setting, general-purpose interrupt processing executes at the interrupt
level set. Therefore, if only using the interrupt for starting the micro DMA (Not using the interrupts as a gen-
eral-purpose interrupt: Level 1 to 6), first set the interrupts level to 0 (Interrupt requests disabled).
If using micro DMA and general-purpose interrupts together, first set the level of the interrupt used to start
micro DMA processing lower than all the other interrupt levels. (Note) In this case, the cause of general inter-
rupt is limited to the edge interrupt.
The priority of the micro DMA transfer end interrupt (INTTC0 to INTTC3) is defined by the interrupt level
and the default priority as the same as the other maskable interrupt.
If a micro DMA request is set for more than one channel at the same time, the priority is not based on the
interrupt priority level but on the channel number. The smaller channel number has the higher priority (Chan-
nel 0 (High) > Channel 3 (Low)).
While the register for setting the transfer source/transfer destination addresses is a 32-bit control register, this
register can only effectively output 24-bit addresses. Accordingly, micro DMA can access 16 Mbytes (The
upper eight bits of the 32 bits are not valid).
Note:If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows.
In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking "Interrupt
specified by micro DMA start vector" (in the Figure 3-1) and reading interrupt vector with setting below, the
vector shifts to that of INTyyy at the time.
This is because the priority level of INTyyy is higher than that of INTxxx.
In the interrupt routine, CPU reads the vector of INTyyy because checking of micro DMA has been finished.
And INTyyy is generated regardless of transfer counter of micro DMA.
INTxxx: level 1 without micro DMA
INTyyy: level 6 with micro DMA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMP91FW60FG(JZ) | 功能描述:16位微控制器 - MCU TLCS900/L1 128K Flash RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| TMP91FW60GF(B,CJZ) | 制造商:Toshiba America Electronic Components 功能描述:IC MCU 16BIT FLASH 128KB 100LQFP |
| TMP91FY12AF | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:Quality And Reliability Assurance / Handling Precautions |
| TMP91FY22F | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:Quality And Reliability Assurance / Handling Precautions |
| TMP91FY22FG | 功能描述:IC MCU FLASH 16BIT 256K 100QFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:TLCS-900/L1 標(biāo)準(zhǔn)包裝:330 系列:- 核心處理器:- 芯體尺寸:8/16-位 速度:40MHz 連通性:UART/USART 外圍設(shè)備:DMA，PWM，WDT 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類型:外部程序存儲(chǔ)器 EEPROM 大小:- RAM 容量:- 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:100-BQFP 包裝:管件 |
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