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參數(shù)資料
| 型號： | TMPR3922AU |
| 廠商： | Toshiba Corporation |
| 英文描述： | 32-bit RISC Microprocessor for PDA（Personal Digital Assistants)(32位 精簡指令集系統(tǒng)計(jì)算機(jī)微處理器，用于掌上電腦PDA) |
| 中文描述： | 32位RISC微處理器的PDA（個(gè)人數(shù)字助理）（32位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器，用于掌上電腦PDA）的 |
| 文件頁數(shù)： | 12/45頁 |
| 文件大?。?/td> | 343K |
| 代理商： | TMPR3922AU |
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2-FEB-1999
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45
TMPR3922AU
Power Supply Pins
NAME
ONBUTN
I/O
I
DESCRIPTION
This pin is used as the On Button for the system. Asserting this signal will
cause PWRCS to set to indicate to the System Power Supply to turn power on
to the system. PWRCS will not assert if the PWROK signal is low.
This pin is used as the chip select for the System Power Supply. When the
system is off, the assertion of this signal will cause the System Power Supply
to turn VCCDRAM
and VCC3 on to power up the system. The Power Supply
will latch SPI commands on the falling edge of PWRCS.
This pin provides a status from the System Power Supply that there is a good
source of power in the system. This signal typically will be asserted if there is a
Battery Charger supplying current or if the Main Battery is good and the Battery
Door is closed. If PWROK is low when the system is powered off, PWRCS will
not assert as a result of the user pressing the ONBUTN or an interrupt
attempting to wake up the system. If the device is on when the PWROK signal
goes low, the software will immediately shut down the system since power is
about to be lost. When PWROK goes low, there must be ample warning so that
the software can shut down the system before power is actually lost.
This pin is used by the System Power Supply to alert the software that some
status has changed in the System Power Supply and the software should read
the status from the System Power Supply to find out what has changed. These
will be low priority events, unlike the PWROK status, which is a high priority
emergency case.
This pin provides the status of the power supply for the ROM, TC35143F,
system buffers, and other transient components in the system. This signal will
be asserted by the System Power Supply when PWRCS is asserted, and will
always be turned off when the system is powered down.
This signal provides power for the DRAM and/or SDRAM. This supply must be off
when VSTANDBY is first asserted, and remain off until the system is powered up by the
assertion of PWRCS. When the software subsequently powers down the system it may
choose to keep this supply on to preserve the contents of memory.
PWRCS
O
PWROK
I
PWRINT
I
VCC3
I
VCCDRAM :
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