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參數(shù)資料
| 型號： | TMPR3922AU |
| 廠商： | Toshiba Corporation |
| 英文描述： | 32-bit RISC Microprocessor for PDA（Personal Digital Assistants)(32位 精簡指令集系統(tǒng)計(jì)算機(jī)微處理器，用于掌上電腦PDA) |
| 中文描述： | 32位RISC微處理器的PDA（個人數(shù)字助理）（32位精簡指令集系統(tǒng)計(jì)算機(jī)微處理器，用于掌上電腦PDA）的 |
| 文件頁數(shù)： | 25/45頁 |
| 文件大?。?/td> | 343K |
| 代理商： | TMPR3922AU |
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TMPR3922AU
5.2.3 MEMORY MANAGEMENT
The TX3920 Processor Core has a 4G-byte memory address space. The 4G-byte memory space
consists of a 2G-byte user area and a 2G-byte kernel area. The kernel area contains a cache area and
an uncache area.The TX3920 Processor Core provides a full-featured memory management unit
(MMU) utilizing an on-chip Translation Lookaside Buffer (TLB). The on-chip TLB majur
characteristics are :
64
×
64-bit wide entries
4K / 16K / 64K / 256K / 1M / 4M page size
fully associative
2 entry micro TLB for instruction address translation
instruction address translation accesses full TLB after micro-TLB miss
data address translation accesses full TLB
5.2.4 PIPELINE
The TX3920 Processor Core pipeline consists of five stages. The pipeline configuration enables the
TX3920 Processor Core to execute nearly all instructions in one clock.
5.2.5 CACHE
The TMPR3922AU incorporates a 16K-byte instruction cache and an 8K-byte data cache. The
instruction cache uses two-way set-associative mapping with a block size of 16 bytes. The data cache
uses two-way set-associative mapping with a block size of four bytes. Both data and Instruction cache
have a lock function that locks data in one direction. Either copy-back or write-through method is used
to write data back to memory.
5.2.6 DSP FUNCTION
The TX3920 Processor Core has a high-speed multiplier/accumulator and supports 32-bit
×
32-bit
multiplier operations, with 64-bit accumulator in one cycle.
5.3 PERIPHERAL FUNCTIONS
5.3.1 CLOCK GENERATOR
The TMPR3922AU uses an internal PLL and an external crystal oscillator to generate a clock with 16
times the input clock frequency. The PLL oscillation can be halted externally to reduce power
dissipation.
5.3.2 WRITE BUFFER
The TMPR3922AU incorporates a four-stage write buffer.
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