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參數(shù)資料
| 型號： | TMS27C040-15 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Programmable Read-Only Memory(512K×8結(jié)構(gòu),可擦可編程只讀存儲器) |
| 中文描述： | 可編程只讀存儲器（為512k × 8結(jié)構(gòu)，可擦可編程只讀存儲器） |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 236K |
| 代理商： | TMS27C040-15 |
TMS27C040 4194304-BIT UV ERASABLE PROGRAMMABLE
TMS27PC040 4194304-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS040E – NOVEMBER 1990 – REVISED JUNE 1995
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
description (continued)
The TMS27C040 is offered in a 600-mil ceramic dual-in-line package (J suffix). The TMS27C040 is offered with
two choices of temperature ranges of 0
°
C to 70
°
C (JL suffix) and – 40
°
C to 85
°
C (JE suffix). The TMS27C040
is also offered with 168-hour burn-in on both temperature ranges (JL4 and JE4 suffixes). (See table below.)
The TMS27PC040 is offered in a 32-lead plastic leaded chip carrier package (FM suffix). The TMS27PC040
is characterized for operation from 0
°
C to 70
°
C (FML suffix).
FUNCTION
SUFFIX FOR OPERATING
TEMPERATURE RANGES
WITHOUT PEP4 BURN-IN
0
°
C TO 70
°
C
JL
SUFFIX FOR OPERATING
TEMPERATURE RANGES WITH
PEP4 168 HR. BURN-IN
0
°
C TO 70
°
C
JL4
–40
°
C TO 85
°
C
JE
–40
°
C TO 85
°
C
JE4
TMS27C040-XXX
TMS27PC040-XXX
FML
These EPROMs and PROMS operate from a single 5-V supply (in the read mode), and they are ideal for use
in microprocessor-based systems. One other (13 V) supply is needed for programming. All programming
signals are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation
The seven modes of operation are listed in the following table. The read mode requires a single 5-V supply. All
inputs are TTL level except for V
PP
during programming (13 V), and V
H
(12 V) on A9 for the signature mode.
MODE
FUNCTION
E
G
VIL
VIH
X
VPP
VCC
VCC
VCC
VPP
VPP
VPP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
A9
X
A0
X
DQ0–DQ7
Data Out
Read
VIL
VIL
VIH
VIL
VIH
VIH
Output Disable
X
X
Hi-Z
Standby
X
X
Hi-Z
Programming
VIH
VIH
VIL
X
X
Data In
Program Inhibit
X
X
Hi-Z
Verify
X
X
Data Out
Signature Mode
VIL
VIL
VCC
VCC
VIL
VIH
MFG Code 97
VH
Device Code 50
X can be VIL or VIH
VH = 12 V
±
0.5 V
read/output disable
When the outputs of two or more TMS27C040s or TMS27PC040s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs of the
other devices. To read the output of a single device, a low level signal is applied to the E and G pins. All other
devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.
latchup immunity
Latchup immunity on the TMS27C040 and TMS27PC040 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the EPROM
is interfaced to industry standard TTL or MOS logic devices. The input/output layout approach controls latchup
without compromising performance or packing density.
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