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TMS320C242
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
13
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
digital I/O and shared pin functions
The ’C242 has a total of 26 general-purpose, bidirectional, digital I/O (GPIO) pins –most of which are shared
between primary functions and I/O. Twenty (20) I/O pins of the ’C242 are shared with other functions. The digital
I/O ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O
and shared pin functions are controlled using eight 16-bit registers. These registers are divided into two types:
Output Control Registers — used to control the multiplexer selection that chooses between the primary
function of a pin or the general-purpose I/O function.
Data and Control Registers — used to control the data and data direction of bidirectional I/O pins.
description of shared I/O pins
The control structure for shared I/O pins is shown in Figure 3, where each pin has three bits that define its
operation:
Mux control bit — this bit selects between the primary function (1) and I/O function (0) of the pin.
I/O direction bit — if the I/O function is selected for the pin (mux control bit is set to 0), this bit determines
whether the pin is an input (0) or an output (1).
I/O data bit — if the I/O function is selected for the pin (mux control bit is set to 0) and the direction selected
is an input, data is read from this bit; if the direction selected is an output, data is written to this bit.
The mux control bit, I/O direction bit, and I/O data bit are in the I/O control registers.
Primary
Function
Pin
(Read/Write)
IOP Data Bit
In
Out
0 = Input
1 = Output
0
1
MUX Control Bit
0 = I/O Function
1 = Primary Function
IOP DIR Bit
Primary
Function
or I/O Pin
When the MUX control bit = 1, the primary
function is selected in all cases except
for the following pins:
1. XF/IOPC0 (0 = Primary Function)
2. BIO/IOPC1 (0 = Primary Function)
3. CLKOUT/IOPD0 (0 = Primary Function)
Note:
Figure 3. Shared Pin Configuration
A summary of shared pin configurations and associated bits is shown in Table 3.
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