參數(shù)資料
型號： TMS320C241
元件分類： 數(shù)字信號處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號處理器
文件頁數(shù)： 48/66頁
文件大?。?/td> 803K
代理商： TMS320C241
TMS320C242
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
48
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
external reference crystal/clock with PLL circuit enabled
timings with the PLL circuit enabled
PARAMETER
MIN
TYP
MAX
UNIT
MHz
fx
Input clock frequency
Oscillator/Resonator
1
5
CLKIN
1
5
MHz
C1, C2
Load capacitance
10
pF
switching characteristics over recommended operating conditions [H = 0.5 t
c(CO)
] (see Figure 18)
PARAMETER
CLOCK MODE
MIN
TYP
MAX
UNIT
tc(CO)
tf(CO)
tr(CO)
tw(COL)
tw(COH)
Cycle time, CLKOUT
50
ns
Fall time, CLKOUT
4
ns
Rise time, CLKOUT
4
ns
Pulse duration, CLKOUT low
H–3
H
H+3
ns
Pulse duration, CLKOUT high
H –3
H
H+3
ns
tp
Transition time, PLL synchronized after PLL enabled
before PLL lock,
CLKIN multiply by 4
2500tc(Cl)
ns
timing requirements (see Figure 18)
EXTERNAL REFERENCE
CRYSTAL
MIN
MAX
UNIT
tc(Cl)
tf(Cl)
tr(Cl)
tw(CIL)
tw(CIH)
This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is
characterized at frequencies approaching 0 Hz, but is tested at fclk = 6.7 MHz to meet device test time requirements.
NOTE: Timings assume CLKOUT is set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset.Timings assume CLKOUT is
set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset.
Cycle time, XTAL1/CLKIN
5 MHz
200
ns
Fall time, XTAL1/CLKIN
5
ns
Rise time, XTAL1/CLKIN
5
ns
Pulse duration, XTAL1/CLKIN low as a percentage of tc(Cl)
Pulse duration, XTAL1/CLKIN high as a percentage of tc(Cl)
40
60
%
40
60
%
XTAL1/CLKIN
CLKOUT
tc(CI)
tw(CIL)
tw(CIH)
tf(Cl)
tr(Cl)
tw(COL)
tw(COH)
tc(CO)
tr(CO)
tf(CO)
tf(CO)
Figure 18. CLKIN-to-CLKOUT Timing for PLL Oscillator Mode, Multiply-by-4 Option with 5-MHz Clock
A
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