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參數(shù)資料
| 型號： | TMS320C242PGS |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 30/66頁 |
| 文件大小： | 803K |
| 代理商： | TMS320C242PGS |
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TMS320C242
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
30
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
dual-access RAM (DARAM)
There are 544 words
×
16 bits of DARAM on the ’C242 device. The ’C242 DARAM allows writes to and reads
from the RAM in the same cycle. The DARAM is configured in three blocks: block 0 (B0), block 1 (B1), and
block 2 (B2). Block 1 contains 256 words and Block 2 contains 32 words, and both blocks are located only in
data memory space. Block 0 contains 256 words, and can be configured to reside in either data or program
memory space. The SETC CNF (configure B0 as data memory) and CLRC CNF (configure B0 as program
memory) instructions allow dynamic configuration of the memory maps through software.
When using on-chip RAM, or high-speed external memory, the ’C242 runs at full speed with no wait states. The
ability of the DARAM to allow two accesses to be performed in one cycle, coupled with the parallel nature of
the ’C242 architecture, enables the device to perform three concurrent memory accesses in any given machine
cycle. Externally, the READY line can be used to interface the ’C242 to slower, less expensive external memory.
Downloading programs from slow off-chip memory to on-chip RAM can speed processing while cutting system
costs.
ROM
The ’C242 device contains 4K words of mask-programmable ROM located in program memory space.
Customers can arrange to have this ROM programmed with contents unique to any particular application.
peripherals
The integrated peripherals of the TMS320x24x are described in the following subsections:
Event-manager (EV2) module
Analog-to-digital converter (ADC) module
Serial communications interface (SCI) module
Watchdog (WD) timer module
event-manager (EV2) module
The event-manager module includes general-purpose (GP) timers, full compare/PWM units, capture units, and
quadrature-encoder pulse (QEP) circuits. Figure 9 shows the functions of the event manager.
A
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相關(guān)代理商/技術(shù)參數(shù) |
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| TMS320C25 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SECOND-GENERATION DIGITAL SIGNAL PROCESSORS |
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| TMS320C25FNA | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Digital Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320C25FNA50 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DIGITAL SIGNAL PROCESSORS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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