參數(shù)資料
型號: TMS320C6414TBZLZA7
廠商: Texas Instruments
文件頁數(shù): 127/146頁
文件大?。?/td> 0K
描述: IC FIXED-POINT DSP 532-FCBGA
標(biāo)準(zhǔn)包裝: 60
系列: TMS320C6414T/15T/16T
類型: 定點
接口: 主機接口,McBSP,PCI,UTOPIA
時鐘速率: 720MHz
非易失內(nèi)存: 外部
芯片上RAM: 1.03MB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 532-BFBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 532-FCBGA(23x23)
包裝: 托盤
配用: TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
81
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
timing requirements for CLKIN for -850 devices§ (see Figure 16)
850
NO.
PLL MODE x20
PLL MODE x12
PLL MODE x6
x1 (BYPASS)
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
1
tc(CLKIN)
Cycle time, CLKIN
23.5
40
14
23.8
13.3
23.8
0
10
ns
2
tw(CLKINH) Pulse duration, CLKIN high
0.4C
0.45C
ns
3
tw(CLKINL)
Pulse duration, CLKIN low
0.4C
0.45C
ns
4
tt(CLKIN)
Transition time, CLKIN
5
1
ns
5
tJ(CLKIN)
Period jitter, CLKIN
0.02C
ns
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
For more details on the PLL multiplier factors (x6, x12, x20), see the Clock PLL section of this data sheet.
§ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
timing requirements for CLKIN for -1G devices§ (see Figure 16)
1G
NO.
PLL MODE x20
PLL MODE x12
PLL MODE x6
x1 (BYPASS)
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
1
tc(CLKIN)
Cycle time, CLKIN
20
40
13.3
23.8
13.3
23.8
0
10
ns
2
tw(CLKINH) Pulse duration, CLKIN high
0.4C
0.45C
ns
3
tw(CLKINL)
Pulse duration, CLKIN low
0.4C
0.45C
ns
4
tt(CLKIN)
Transition time, CLKIN
5
1
ns
5
tJ(CLKIN)
Period jitter, CLKIN
0.02C
ns
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
For more details on the PLL multiplier factors (x6, x12, x20), see the Clock PLL section of this data sheet.
§ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
CLKIN
2
3
4
5
1
Figure 16. CLKIN Timing
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