參數(shù)資料
型號: TMS320C6414TBZLZA7
廠商: Texas Instruments
文件頁數(shù): 36/146頁
文件大?。?/td> 0K
描述: IC FIXED-POINT DSP 532-FCBGA
標準包裝: 60
系列: TMS320C6414T/15T/16T
類型: 定點
接口: 主機接口,McBSP,PCI,UTOPIA
時鐘速率: 720MHz
非易失內(nèi)存: 外部
芯片上RAM: 1.03MB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 532-BFBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 532-FCBGA(23x23)
包裝: 托盤
配用: TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
130
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
UTOPIA SLAVE TIMING [C6415T AND C6416T ONLY] (CONTINUED)
timing requirements for UTOPIA Slave receive (see Figure 60)
NO.
600, 720
850, 1G
UNIT
NO.
MIN
MAX
UNIT
1
tsu(URDV-URCH)
Setup time, URDATA valid before URCLK high
4
ns
2
th(URCH-URDV)
Hold time, URDATA valid after URCLK high
1
ns
3
tsu(URAV-URCH)
Setup time, URADDR valid before URCLK high
4
ns
4
th(URCH-URAV)
Hold time, URADDR valid after URCLK high
1
ns
9
tsu(URENBL-URCH)
Setup time, URENB low before URCLK high
4
ns
10
th(URCH-URENBL)
Hold time, URENB low after URCLK high
1
ns
11
tsu(URSH-URCH)
Setup time, URSOC high before URCLK high
4
ns
12
th(URCH-URSH)
Hold time, URSOC high after URCLK high
1
ns
switching characteristics over recommended operating conditions for UTOPIA Slave receive
(see Figure 60)
NO.
PARAMETER
600, 720
850, 1G
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
5
td(URCH-URCLAV)
Delay time, URCLK high to URCLAV driven active value
3
12
ns
6
td(URCH-URCLAVL)
Delay time, URCLK high to URCLAV driven inactive low
3
12
ns
7
td(URCH-URCLAVHZ)
Delay time, URCLK high to URCLAV going Hi-Z
9
18.5
ns
8
tw(URCLAVL-URCLAVHZ) Pulse duration (low), URCLAV low to URCLAV Hi-Z
3
ns
P48
H1
H2
H3
N
0x1F
N+1
0x1F
N+2
0x1F
N
N+1
N+2
12
11
9
10
5
4
3
2
1
URCLK
URDATA[7:0]
URADDR[4:0]
URCLAV
URENB
URSOC
The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and
URSOC signals).
8
6
7
Figure 60. UTOPIA Slave Receive Timing
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