參數(shù)資料
型號： TMS320C6415TZLZ7
廠商： Texas Instruments
文件頁數(shù)： 131/146頁
文件大?。?/td> 0K
描述： IC DSP FIXED-POINT 532-FCBGA
標(biāo)準(zhǔn)包裝： 60
系列： TMS320C6414T/15T/16T
類型： 定點
接口： 主機(jī)接口，McBSP，PCI，UTOPIA
時鐘速率： 720MHz
非易失內(nèi)存： 外部
芯片上RAM： 1.03MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： 0°C ~ 90°C
安裝類型： 表面貼裝
封裝/外殼： 532-BFBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 532-FCBGA（23x23）
包裝： 托盤
配用： TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
其它名稱： 296-19387
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
85
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles for EMIFA module§
(see Figure 22 and Figure 23)
NO.
600
720
850
1G
UNIT
MIN
MAX
3
tsu(EDV-AREH)
Setup time, EDx valid before ARE high
6.5
ns
4
th(AREH-EDV)
Hold time, EDx valid after ARE high
1
ns
6
tsu(ARDY-EKO1H)
Setup time, ARDY valid before ECLKOUTx high
3
ns
7
th(EKO1H-ARDY)
Hold time, ARDY valid after ECLKOUTx high
1
ns
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is only recognized
two cycles before the end of the programmed strobe time and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is
recognized low, the end of the strobe time is two cycles after ARDY is recognized high. To use ARDY as an asynchronous input, the pulse width
of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
§ These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous
memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and
BAWE (for EMIFB)].
switching characteristics over recommended operating conditions for asynchronous memory
cycles for EMIFA module§# (see Figure 22 and Figure 23)
NO.
PARAMETER
600
720
850
1G
UNIT
MIN
MAX
1
tosu(SELV-AREL)
Output setup time, select signals valid to ARE low
RS * E 1.5
ns
2
toh(AREH-SELIV)
Output hold time, ARE high to select signals invalid
RH * E 1.9
ns
5
td(EKO1H-AREV)
Delay time, ECLKOUTx high to ARE valid
1
7
ns
8
tosu(SELV-AWEL)
Output setup time, select signals valid to AWE low
WS * E 1.7
ns
9
toh(AWEH-SELIV)
Output hold time, AWE high to select signals invalid
WH * E 1.8
ns
10
td(EKO1H-AWEV)
Delay time, ECLKOUTx high to AWE valid
1.3
7.1
ns
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
§ These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous
memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and
BAWE (for EMIFB)].
E = ECLKOUT1 period in ns for EMIFA or EMIFB
# Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0].
Select signals EMIFB include: BCEx, BBE[1:0], BEA[20:1], BAOE; and for EMIFB writes, include BED[15:0].
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