參數(shù)資料
型號： TMS320DM642GDK500
廠商： Texas Instruments, Inc.
英文描述： Adjustable 2.5-36V +/-2.2% Tolerance, 1-100mA Shunt Regulator - PB Free; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500
中文描述： 視頻/影像定點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 106/123頁
文件大小： 1205K
代理商： TMS320DM642GDK500
www.ti.com
Data Valid
11
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data Must
Be Valid
Master Out Data Is Valid
1
7
6
10
3
2
SPISTE
(A)
6.9.6
SPI Slave Mode Timing
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
A.
In the master mode, SPISTE goes active 0.5t
c(SPC)
(minimum) before valid SPI clock edge. On the trailing end of the
word, the SPISTE will go inactive 0.5t
c(SPC)
after the receiving edge (SPICLK) of the last data bit.
Figure 6-18. SPI Master External Timing (Clock Phase = 1)
Table 6-34
lists the slave mode external timing (clock phase = 0) and
Table 6-35
(clock phase = 1).
Figure 6-19
and
Figure 6-20
show the timing waveforms.
Table 6-34. SPI Slave Mode External Timing (Clock Phase = 0)
(1)(2)(3)(4)(5)
NO.
12
13
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
c(SPC)S
t
w(SPCH)S
t
w(SPCL)S
t
w(SPCL)S
t
w(SPCH)S
t
d(SPCH-SOMI)S
t
d(SPCL-SOMI)S
t
v(SPCL-SOMI)S
t
v(SPCH-SOMI)S
t
su(SIMO-SPCL)S
t
su(SIMO-SPCH)S
t
v(SPCL-SIMO)S
t
v(SPCH-SIMO)S
Cycle time, SPICLKCycle time, SPICLK
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0)
Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1)
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1)
4t
c(LCO)
0.5t
c(SPC)S
- 10
0.5t
c(SPC)S
- 10
0.5t
c(SPC)S
- 10
0.5t
c(SPC)S
- 10
0.5t
c(SPC)S
0.5t
c(SPC)S
0.5t
c(SPC)S
0.5t
c(SPC)S
14
15
35
35
16
0.75t
c(SPC)S
0.75t
c(SPC)S
19
35
35
20
0.5t
c(SPC)S
0.5t
c(SPC)S
(1)
(2)
(3)
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
t
= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
t
= LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
(4)
(5)
106
Electrical Specifications
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參數(shù)描述
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