參數(shù)資料
型號： TMS320DM642GDK500
廠商： Texas Instruments, Inc.
英文描述： Adjustable 2.5-36V +/-2.2% Tolerance, 1-100mA Shunt Regulator - PB Free; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500
中文描述： 視頻/影像定點數(shù)字信號處理器
文件頁數(shù)： 19/123頁
文件大?。?/td> 1205K
代理商： TMS320DM642GDK500
www.ti.com
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
Table 2-2. Signal Descriptions (continued)
PIN NO.
NAME
DESCRIPTION
(1)
PZ PIN
#
2
11
41
49
55
62
69
77
87
89
94
GGM
BALL #
B1
E3
H6
K9
H10
F7
D10
A9
D6
A5
A4
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
Digital Ground Pins
GPIOA AND PERIPHERAL SIGNALS
(2)
General purpose input/output 0 (I/O/Z)
(3)
Enhanced PWM1 Output A and HRPWM channel (O)
-
-
General purpose input/output 1 (I/O/Z)
(3)
Enhanced PWM1 Output B (O)
SPI-D slave in, master out (I/O) (not available on F2801/9501)
-
General purpose input/output 2 (I/O/Z)
(3)
Enhanced PWM2 Output A and HRPWM channel (O)
-
-
General purpose input/output 3 (I/O/Z)
(3)
Enhanced PWM2 Output B (O)
SPI-D slave out, master in (I/O) (not available on F2801/9501)
-
General purpose input/output 4 (I/O/Z)
(3)
Enhanced PWM3 output A and HRPWM channel (O)
-
-
General purpose input/output 5 (I/O/Z)
(3)
Enhanced PWM3 output B (O)
SPI-D clock (I/O) (not available on F2801/9501)
Enhanced capture input/output 1 (I/O)
General purpose input/output 6 (I/O/Z)
(3)
Enhanced PWM4 output A and HRPWM channel (not available on F2801/9501) (O)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
General purpose input/output 7 (I/O/Z)
(3)
Enhanced PWM4 output B (not available on F2801/9501) (O)
SPI-D slave transmit enable (not available on F2801/9501 (I/O)
Enhanced capture input/output 2 (I/O)
General purpose input/output 8 (I/O/Z)
(3)
Enhanced PWM5 output A (not available on F2801/9501) (O)
Enhanced CAN-B transmit (not available on F2806/F2801/9501) (O)
ADC start-of-conversion A (O)
General purpose input/output 9 (I/O/Z)
(3)
Enhanced PWM5 output B (not available on F2801/9501) (O)
SCI-B transmit data (not available on F2801/9501) (O)
Enhanced capture input/output 3 (not available on F2801/9501) (I/O)
GPIO0
EPWM1A
-
-
GPIO1
EPWM1B
SPISIMOD
-
GPIO2
EPWM2A
-
-
GPIO3
EPWM2B
SPISOMID
-
GPIO4
EPWM3A
-
-
GPIO5
EPWM3B
SPICLKD
ECAP1
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO
GPIO7
EPWM4B
SPISTED
ECAP2
GPIO8
EPWM5A
CANTXB
ADCSOCAO
GPIO9
EPWM5B
SCITXDB
ECAP3
47
K8
44
K7
45
J7
48
J8
51
J9
53
H9
56
G9
58
G8
60
F9
61
F8
(2)
All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively
enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at
reset. The peripheral signals that are listed under them are alternate functions.
The pullups on GPIO0-GPIO11 pins are not enabled at reset.
(3)
Introduction
19
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