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| 型號： | TMS320DM648ZUTA8 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 137/190頁 |
| 文件大小： | 0K |
| 描述： | IC DGTL MEDIA PROC 529FCBGA |
| 標(biāo)準包裝： | 84 |
| 系列： | TMS320DM64x, DaVinci™ |
| 類型： | 定點 |
| 接口： | 主機接口，I²C，McASP，PCI，SPI，UART |
| 時鐘速率： | 800MHz |
| 非易失內(nèi)存： | ROM（64 kB） |
| 芯片上RAM： | 576kB |
| 電壓 - 輸入/輸出： | 1.8V，3.3V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 529-BFBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 529-FCBGA（19x19） |
| 包裝： | 托盤 |
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SPRS372H – MAY 2007 – REVISED APRIL 2012
4
System Interconnect
The C64x+ Megamodule, the EDMA3 transfer controllers, and the system peripherals are interconnected
through two switch fabrics. The switch fabrics allow for low-latency, concurrent data transfers between
master peripherals and slave peripherals. Through a switch fabric, the CPU can send data to the video
ports without affecting a data transfer between the PCI and the DDR2 memory controller. The switch
fabrics also allow for seamless arbitration between the system masters when accessing system slaves.
4.1
Internal Buses, Bridges, and Switch Fabrics
Two types of buses exist in the device: data buses and configuration buses. Some device peripherals
have both a data bus and a configuration bus interface, while others only have one type of interface.
Furthermore, the bus interface width and speed varies from peripheral to peripheral. Configuration buses
are mainly used to access the register space of a peripheral and the data buses are used mainly for data
transfers. However, in some cases, the configuration bus is also used to transfer data. For example, data
is transferred to the UART or I2C via their configuration bus. Similarly, the data bus can also be used to
access the register space of a peripheral. For example, the EMIFA and DDR2 memory controller registers
are accessed through their data bus interface.
The C64x+ Megamodule, the EDMA3 traffic controllers, and the various system peripherals can be divided
into two categories: masters and slaves. Masters are capable of initiating read and write transfers in the
system and do not rely on the EDMA3 for their data transfers. Slaves, on the other hand, rely on the
EDMA3 to perform transfers to and from them. Masters include the EDMA3 traffic controllers and PCI.
Slaves include the McASP, video ports, and I2C.
The device contains two switch fabrics through which masters and slaves communicate. The data switch
fabric, known as the data switched central resource (SCR), is a high-throughput interconnect mainly used
to move data across the system (for more information, see Section 4.2). The data SCR connects masters
to slaves via 128-bit data buses running at a SYSCLK1 frequency (SYSCLK1 is generated from PLL1
controller). Peripherals that have a 128-bit data bus interface running at this speed can connect directly to
the data SCR; other peripherals require a bridge.
The configuration switch fabric, also known as the configuration switch central resource (SCR) is mainly
used by the C64x+ Megamodule to access peripheral registers (for more information, see Section 4.3).
The configuration SCR connects the C64x+ Megamodule to slaves via 32-bit configuration buses running
at a SYSCLK1 frequency (SYSCLK1 is generated from the PLL1 controller). As with the data SCR, some
peripherals require the use of a bridge to interface to the configuration SCR. Note that the data SCR also
connects to the configuration SCR. Bridges perform a variety of functions:
Conversion between configuration bus and data bus.
Width conversion between peripheral bus width and SCR bus width
Frequency conversion between peripheral bus frequency and SCR bus frequency
For example, the EMIFA memory controller require a bridge to convert their 64-bit data bus interface into a
128-bit interface so that they can connect to the data SCR.
Some peripherals can be accessed through the data SCR and also through the configuration SCR.
4.2
Data Switch Fabric Connections
Figure 4-1 shows the connection between slaves and masters through the data switched central resource
(SCR). Masters are shown on the right and slaves on the left. The data SCR connects masters to slaves
via 128-bit data buses running at a SYSCLK1 frequency. SYSCLK1 is supplied by the PLL1 controller and
is fixed at a frequency equal to the CPU frequency divided by 3. Some peripherals, like PCI and the
C64x+ Megamodule, have both slave and master ports. Each EDMA3 transfer controller has an
independent connection to the data SCR.
Masters can access the configuration SCR through the data SCR. The configuration SCR is described in
50
System Interconnect
Copyright 2007–2012, Texas Instruments Incorporated
Product Folder Link(s): TMS320DM647 TMS320DM648
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