參數(shù)資料
型號(hào)： TMS320F240PQL
英文描述： 16-Bit Microcontroller
中文描述： 16位微控制器
文件頁(yè)數(shù)： 9/105頁(yè)
文件大?。?/td> 1481K
代理商： TMS320F240PQL
TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
TERMINAL
NAME
TYPE
DESCRIPTION
NO.
SERIAL PERIPHERAL INTERFACE (SPI) AND BIT I/O PINS
SPISIMO/IO
45
I/O
SPI slave in, master out , or general-purpose bidirectional I/O. This pin is configured as a digital
input by all device resets.
SPISOMI/IO
48
I/O
SPI slave out, master in, or general-purpose bidirectional I/O. This pin is configured as a digital
input by all device resets.
SPICLK/IO
49
I/O
SPI clock, or general-purpose bidirectional I/O. This pin is configured as a digital input by all
device resets.
SPISTE/IO
51
I/O
SPI slave transmit enable (optional), or general-purpose bidirectional I/O. This pin is configured
as a digital input by all device resets.
COMPARE SIGNALS
PWM1/CMP1
PWM2/CMP2
PWM3/CMP3
PWM4/CMP4
PWM5/CMP5
PWM6/CMP6
94
95
96
97
98
99
O/Z
Compare units compare or PWM outputs. The state of these pins is determined by the
compare/PWM and the full action control register (ACTR). CMP1–CMP6 go to the high-
impedance state when unmasked PDPINT goes active low, and when reset (RS) is asserted.
INTERRUPT AND MISCELLANEOUS SIGNALS
RS
35
I/O
Reset input. RS causes the TMS320x240 to terminate execution and sets PC = 0. When RS
is brought to a high level, execution begins at location zero of program memory. RS affects (or
sets to zero) various registers and status bits.
MP/MC
37
I
MP/MC (microprocessor/microcomputer) select. If MP/MC is low, internal program memory is
selected. If it is high, external program memory is selected.
NMI
40
I
Nonmaskable interrupt. When NMI is activated, the device is interrupted regardless of the state
of the INTM bit of the status register. NMI has programmable polarity.
PORESET
41
I
Power-on reset. PORESET causes the TMS320x240 to terminate execution and sets PC = 0.
When PORESET is brought to a high level, execution begins at location zero of program
memory. PORESET affects (or sets to zero) the same registers and status bits as RS. In addi-
tion, PORESET initializes the PLL control registers.
XINT1
53
I
External user interrupt no. 1
XINT2/IO
54
I/O
External user interrupt no. 2. General-purpose bidirectional I/O. This pin is configured as a
digital input by all device resets.
XINT3/IO
55
I/O
External user interrupt no. 3. General-purpose bidirectional I/O. This pin is configured as a
digital input by all device resets.
PDPINT
52
I
Maskable power-drive protection interrupt. If PDPINT is unmasked and it goes active low, the
timer compare outputs immediately go to the high-impedance state.
CLOCK SIGNALS
XTAL2
57
O
PLL oscillator output. XTAL2 is tied to one side of a reference crystal when the device is in PLL
mode (CLKMD[1:0] = 1x, CKCR0.7–6). This pin can be left unconnected in oscillator bypass
mode (OSCBYP
≤
VIL). This pin goes in the high-impedance state when EMU1/OFF is active
low.
XTAL1/CLKIN
58
I/Z
PLL oscillator input. XTAL1/CLKIN is tied to one side of a reference crystal in PLL mode
(CLKMD[1:0] = 1x, CKCR0.7–6), or is connected to an external clock source in oscillator
bypass mode (OSCBYP
≤
VIL).
Bypass oscillator if low
OSCBYP
I = input, O = output, Z = high impedance
56
I
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