td(IDLEXCOL) X1/X2 or XCLKIN XCLKOUT HALT Wake-up Latency Flushing Pipeline t
參數(shù)資料
型號: TMS320F28069PZPQ
廠商: Texas Instruments
文件頁數(shù): 61/174頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 256KB FLSH 100HTQFP
產品培訓模塊: ControlSUITE
Piccolo F2806x
TPS75005 Single IC Power for C2000 MCU
標準包裝: 1,000
系列: TMS320F2806x, Piccolo™, C2000™
核心處理器: C28x
芯體尺寸: 32-位
速度: 80MHz
連通性: CAN,I²C,McBSP,SCI,SPI,UART/USART
外圍設備: 欠壓檢測/復位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 54
程序存儲器容量: 256KB(128K x 16)
程序存儲器類型: 閃存
RAM 容量: 50K x 16
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 1.995 V
數(shù)據(jù)轉換器: A/D 16x12b
振蕩器型: 內部
工作溫度: -40°C ~ 125°C
封裝/外殼: 100-TQFP 裸露焊盤
包裝: 托盤
td(IDLEXCOL)
X1/X2 or
XCLKIN
XCLKOUT
HALT
Wake-up Latency
Flushing Pipeline
td(WAKEHALT
Device
Status
PLL Lock-up Time
Normal
Execution
tw(WAKE-GPIO)
GPIOn
(I)
Oscillator Start-up Time
(A)
(G)
(C)
(D)(E)
(F)
(B)
(H)
)
t
p
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
A.
IDLE instruction is executed to put the device into HALT mode.
B.
The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before
oscillator is turned off and the CLKIN to the core is stopped:
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly.
C.
Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the
watchdog alive in HALT mode. This is done by writing to the appropriate bits in the CLKCTL register. After the IDLE
instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the wake-up signal could be
asserted.
D.
When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator
wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This
enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin
asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to
entering and during HALT mode.
E.
The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.
F.
Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms.
G.
When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.
H.
Normal operation resumes.
I.
From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 5-56. HALT Wake-Up Using GPIOn
Copyright 2010–2012, Texas Instruments Incorporated
Peripheral and Electrical Specifications
153
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