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參數(shù)資料
| 型號： | TMS320M642AGDK6 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1A, 52kHz (250kHz Max) Current Mode PWM Control Circuit with 8.4V UVLO Threshold and 96% Max Duty Cycle; Package: SOIC 14 LEAD; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2500 |
| 中文描述： | 視頻/影像定點數(shù)字信號處理器 |
| 文件頁數(shù)： | 90/123頁 |
| 文件大?。?/td> | 1205K |
| 代理商： | TMS320M642AGDK6 |
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C4
C3
XCLKOUT
(B)
XCLKIN
(A)
C5
C9
C10
C1
C8
C6
6.7
Power Sequencing
6.7.1
Power Management and Supervisory Circuit Solutions
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
A.
The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is
intended to illustrate the timing parameters only and may differ based on actual configuration.
XCLKOUT configured to reflect SYSCLKOUT.
B.
Figure 6-4. Clock Timing
No requirements are placed on the power up/down sequence of the various power pins to ensure the
correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers
of the I/O pins are powered prior to the 1.8-V transistors, it is possible for the output buffers to turn on,
causing a glitch to occur on the pin during power up. To avoid this behavior, power the V
DD
pins prior to or
simultaneously with the V
DDIO
pins, ensuring that the V
DD
pins have reached 0.7 V before the V
DDIO
pins
reach 0.7 V.
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for t
w(RSL1)
after the input clock is stable (see
Table 6-11
). This is to enable the entire device to start from a known condition.
2. During power down, the XRS pin must be pulled low at least 8
μ
s prior to V
DD
reaching 1.5 V. This is to
enhance flash reliability.
Additionally it is recommended that no voltage larger than a diode drop (0.7 V) should be applied to any
pin prior to powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n
junctions in unintended ways and produce unpredictable results.
Table 6-10
lists the power management and supervisory circuit solutions for 280x DSPs. LDO selection
depends on the total power consumed in the end application. Go to www.power.ti.com for a complete list
of TI power ICs or select TI DSP Power Solutions for links to the
DSP Power Selection Guide
(slub006a.pdf) and links to specific power reference designs.
Table 6-10. Power Management and Supervisory Circuit Solutions
SUPPLIER
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
TYPE
LDO
LDO
LDO
SVS
SVS
LDO
LDO
DC/DC
DC/DC
PART
DESCRIPTION
Dual 1-A low-dropout regulator (LDO) with supply voltage supervisor (SVS)
Dual 500/250-mA LDO with SVS
250-mA LDO with PG
Open Drain SVS with programmable delay
Low-cost Open-drain SVS with 5
μ
S delay
200-mA LDO in WCSP package
400-mA LDO with 40 mV of V
DO
High V
in
1.2-A dc/dc converter in 4x4 QFN package
500-mA converter in WCSP package
TPS767D301
TPS70202
TPS766xx
TPS3808
TPS3803
TPS799xx
TPS736xx
TPS62110
TPS6230x
Electrical Specifications
90
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