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參數(shù)資料
| 型號(hào)： | TMS320M642AZNZ5 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1A, 52kHz (250khz Max) Current Mode PWM Control Circuit with 16V UVLO Threshold and 48% Max Duty Cycle<sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup><sup>3</sup> ; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500 |
| 中文描述： | 視頻/影像定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 32/123頁 |
| 文件大小： | 1205K |
| 代理商： | TMS320M642AZNZ5 |
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3.2.16
Peripheral Frames 0, 1, 2 (PFn)
3.2.17
General-Purpose Input/Output (GPIO) Multiplexer
3.2.18
32-Bit CPU-Timers (0, 1, 2)
3.2.19
Control Peripherals
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
The 280x segregate peripherals into three sections. The mapping of peripherals is as follows:
PF0:
PIE:
Flash:
Timers:
CSM:
ADC:
eCAN:
GPIO:
ePWM:
eCAP:
eQEP:
SYS:
SCI:
SPI:
ADC:
I
2
C:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash Control, Programming, Erase, Verify Registers
CPU-Timers 0, 1, 2 Registers
Code Security Module KEY Registers
ADC Result Registers (dual-mapped)
eCAN Mailbox and Control Registers
GPIO MUX Configuration and Control Registers
Enhanced Pulse Width Modulator Module and Registers
Enhanced Capture Module and Registers
Enhanced Quadrature Encoder Pulse Module and Registers
System Control Registers
Serial Communications Interface (SCI) Control and RX/TX Registers
Serial Port Interface (SPI) Control and RX/TX Registers
ADC Status, Control, and Result Register
Inter-Integrated Circuit Module and Registers
PF1:
PF2:
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins
are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is
reserved for Real-Time OS (RTOS)/BIOS applications. CPU-Timer 1 is also reserved for TI system
functions. CPU-Timer 2 is connected to INT14 of the CPU. CPU-Timer 1 can be connected to INT13 of
the CPU. CPU-Timer 0 is for general use and is connected to the PIE block.
The 280x devices support the following peripherals which are used for embedded control and
communication:
ePWM:
The enhanced PWM peripheral supports independent/complementary PWM generation,
adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip
mechanism. Some of the PWM pins support HRPWM features.
The enhanced capture peripheral uses a 32-bit time base and registers up to four
programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
eCAP:
32
Functional Overview
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