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| 型號： | TMS320UVC5402 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processor(定點DSP) |
| 中文描述： | 定點數(shù)字信號處理器（定點DSP）的 |
| 文件頁數(shù)： | 24/60頁 |
| 文件大?。?/td> | 772K |
| 代理商： | TMS320UVC5402 |
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TMS320UVC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS100A – APRIL 1999 – REVISED AUGUST 1999
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
McBSP control registers and subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location.
The serial port subbank address (SPSA) register is used as a pointer to select a particular register within the
subbank. The serial port subbank data (SPSD) register is used to access (read or write) the selected register.
Table 11 shows the McBSP control registers and their corresponding subaddresses.
Table 11. McBSP Control Registers and Subaddresses
McBSP0
McBSP1
NAME
ADDRESS
NAME
ADDRESS
SUB-
ADDRESS
DESCRIPTION
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áááááááááááááááááááááááááááááááá
MCR10
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
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DMA subbank addressed registers
SPCR10
39h
39h
MCR11
SPCR11
49h
49h
08h
00h
Multichannel register 1
Serial port control register 1
SPCR20
39h
SPCR21
49h
01h
Serial port control register 2
P
áááááááááááááááááááááááááááááááá
SRGR10
39h
SRGR11
49h
06h
Sample rate generator register 1
SRGR20
MCR20
39h
39h
SRGR21
MCR21
49h
49h
07h
09h
Sample rate generator register 2
Multichannel register 2
RCERA0
39h
RCERA1
49h
0Ah
Receive channel enable register partition A
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The direct memory access (DMA) controller has several control registers associated with it. The main control
register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using
the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single
memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular register
within the subbank, while the DMA subbank data (DMSDN) register or the DMA subbank data register with
autoincrement (DMSDI) is used to access (read or write) the selected register.
When the DMSDI register is used to access the subbank, the subbank address is automatically
postincremented so that a subsequent access affects the next register within the subbank. This autoincrement
feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature
is not required, the DMSDN register should be used to access the subbank. Table 12 shows the DMA controller
subbank addressed registers and their corresponding subaddresses.
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