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參數(shù)資料
| 型號(hào)： | TMS320UVC5402 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Fixed-Point Digital Signal Processor(定點(diǎn)DSP) |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器（定點(diǎn)DSP）的 |
| 文件頁數(shù)： | 9/60頁 |
| 文件大小： | 772K |
| 代理商： | TMS320UVC5402 |
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TMS320UVC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS100A – APRIL 1999 – REVISED AUGUST 1999
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
memory
The ’UVC5402 device provides both on-chip ROM and RAM memories to aid in system performance and
integration.
on-chip ROM with bootloader
The ’UVC5402 features a 4K-word
×
16-bit on-chip maskable ROM. Customers can arrange to have the ROM
of the ’UVC5402 programmed with contents unique to any particular application.
A bootloader is available in the standard ’UVC5402 on-chip ROM. This bootloader can be used to automatically
transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC pin
is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location
contains a branch instruction to the start of the bootloader program. The standard ’UVC5402 bootloader
provides different ways to download the code to accomodate various system requirements:
Parallel from 8-bit or 16-bit-wide EPROM
Parallel from I/O space 8-bit or 16-bit mode
Serial boot from serial ports 8-bit or 16-bit mode
Host-port interface boot
The standard on-chip ROM layout is shown in Table 1.
Table 1. Standard On-Chip ROM Layout
ADDRESS RANGE
DESCRIPTION
F000h – F7FFh
Reserved
F800h – FBFFh
Bootloader
FC00h – FCFFh
μ
-law expansion table
FD00h – FDFFh
A-law expansion table
FE00h – FEFFh
Sine look-up table
FF00h – FF7Fh
Reserved
FF80h – FFFFh
Interrupt vector table
In the ’UVC5402 ROM, 128 words are reserved for factory device-testing purposes. Application
code to be implemented in on-chip ROM must reserve these 128 words at addresses
FF00h–FF7Fh in program space.
on-chip RAM
The ’UVC5402 device contains 16K
×
16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed
of two blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and
a write in one cycle. The DARAM is located in the address range 0080h–3FFFh in data space, and can be
mapped into program/data space by setting the OVLY bit to one.
P
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