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參數(shù)資料
| 型號： | TMS320VC5409PGE-100 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 9/78頁 |
| 文件大小： | 1018K |
| 代理商： | TMS320VC5409PGE-100 |
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TMS320VC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS082C – APRIL 1999 – REVISED MARCH 2000
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
NAME
DESCRIPTION
I/O
INTERNAL
PIN STATE
TERMINAL
HOST-PORT INTERFACE SIGNALS
SECONDARY
PRIMARY
HA15 – HA0
Bus holders
available
I/O/Z
A15 – A0
O/Z
These pins can be used to address internal memory via the HPI
when the HPI16 pin is high. The sixteen address pins, A15 to A0,
are multiplexed to transfer address between the core CPU and
external data/program memory, I/O devices, or HPI in 16-bit mode.
The address bus includes bus holders to reduce the static power
dissipation caused by floating, unused pins. The bus holders also
eliminate the need for external bias resistors on unused pins. When
the address bus is not being driven by the ’5409, the bus holders
keep the pins at the logic level that was most recently driven. The
address bus holders of the ’5409 are disabled at reset, and can be
enabled/disabled via the HBH bit of the BSCR.
HD15 – HD0
Bus holders
available
I/O/Z
D15 – D0
O/Z
These pins can be used to read/write internal memory via the HPI
when the HPI16 pin is high. The sixteen data pins, D15 to D0, are
multiplexed to transfer data between the core CPU and external
data/program memory, I/O devices, or HPI in 16-bit mode. The data
bus is placed in the high-impedance state when not outputting or
when RS or HOLD is asserted. The data bus also goes into the
high-impedance state when OFF is low.
The data bus includes bus holders to reduce the static power
dissipation caused by floating, unused pins. The bus holders also
eliminate the need for external bias resistors on unused pins. When
the data bus is not being driven by the ’5409, the bus holders keep
the pins at the logic level that was most recently driven. The data
bus holders of the ’5409 are disabled at reset, and can be
enabled/disabled via the BH bit of the BSCR.
HD7 – HD0
Bus holders
available
I/O/Z
Parallel bidirectional data bus. When the HPI is disabled or when the HPI16 pin is high, these pins
can also be used as general-purpose I/O pins. HD7–HD0 are placed in the high-impedance state
when not outputting data or when OFF is low.
The HPI data bus includes bus holders to reduce the static power dissipation caused by floating,
unused pins. When the HPI data bus is not being driven by the ’5409, the bus holders keep the pins
at the logic level that was most recently driven. The HPI data bus holders are disabled at reset. In
8-bit mode the bus holders can be enabled/disabled via the HBH bit of the BSCR. In 16-bit mode
the bus holders are always active on the HD7–HD0 pins.
HCNTL0
HCNTL1
Pullup
resistor
I
Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control
inputs have internal pullup resistors that are only enabled when HPIENA = 0.
HBIL
Pullup
resistor
I
Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal
pullup resistor that is only enabled when HPIENA = 0.
HCS
Schmitt
trigger/pullup
resistor
I
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The
chip-select input has an internal pullup resistor that is only enabled when HPIENA = 0.
HDS1
HDS2
Schmitt
trigger/pullup
resistor
I
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers.
The strobe inputs have internal pullup resistors that are only enabled when HPIENA = 0.
HAS
Schmitt
trigger/pullup
resistor
I
Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in
the HPIA register. HAS has an internal pullup resistor that is only enabled when HPIENA = 0.
I = Input, O = Output, Z = High-impedance, S = Supply
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS320VC5409PGE100 | 制造商:Texas Instruments 功能描述:Digital Signal Processor IC |
| TMS320VC5409PGE-80 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320VC5409ZGU100 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320VC5409ZGU-80 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320VC5410AGGU1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
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