參數(shù)資料
型號: TMS32C6205DZHKA200
廠商: Texas Instruments
文件頁數(shù): 42/73頁
文件大小: 0K
描述: IC FIXED POINT DSP 288-BGA
標(biāo)準(zhǔn)包裝: 1
系列: TMS320C62x
類型: 定點
接口: McBSP,PCI
時鐘速率: 200MHz
非易失內(nèi)存: 外部
芯片上RAM: 128kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.50V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 288-LFBGA
供應(yīng)商設(shè)備封裝: 288-BGA Microstar(16x16)
包裝: 托盤
TMS320C6205
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SPRS106G OCTOBER 1999 REVISED JULY 2006
47
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles (see Figure 27)
NO.
200
UNIT
NO.
MIN
MAX
UNIT
3
toh(HOLDAL-HOLDL) Output hold time, HOLD low after HOLDA low
P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles
(see Figure 27)
NO.
PARAMETER
200
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
1
td(HOLDL-EMHZ)
Delay time, HOLD low to EMIF Bus high impedance
4P
§
ns
2
td(EMHZ-HOLDAL)
Delay time, EMIF Bus high impedance to HOLDA low
0
2P
ns
4
td(HOLDH-EMLZ)
Delay time, HOLD high to EMIF Bus low impedance
3P
7P
ns
5
td(EMLZ-HOLDAH)
Delay time, EMIF Bus low impedance to HOLDA high
0
2P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
§ All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with
external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the
minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
HOLD
HOLDA
EMIF Bus
DSP Owns Bus
External Requestor
Owns Bus
DSP Owns Bus
C6205
1
3
25
4
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
Figure 27. HOLD/HOLDA Timing
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