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參數(shù)資料
| 型號： | TMS416100-60DJ |
| 英文描述： | x1 Fast Page Mode DRAM |
| 中文描述： | x1快速頁面模式的DRAM |
| 文件頁數(shù)： | 4/25頁 |
| 文件大小： | 437K |
| 代理商： | TMS416100-60DJ |
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
write enable (W)
The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL
circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out remains in the high-impedance state for the entire cycle, permitting common
I/O operation.
data in (D)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS is already low and the data is strobed in by W with setup and hold times referenced
to this signal.
data out (Q)
The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. The output is in the high-impedance (floating) state until CAS is brought low. In a read cycle,
the output becomes valid at the latest occurrence of t
RAC
, t
AA
, t
CAC
, or t
CPA
and remains valid while CAS is low.
CAS going high returns it to the high-impedance state.
refresh
A refresh operation must be performed at least once every 64 ms to retain data. This can be achieved by strobing
each of the 4096 rows (A0–A11). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh. Hidden refresh can be performed by holding CAS at V
IL
after a read operation and cycling RAS after
a specified precharge period, similar to a RAS-only refresh cycle except with CAS held low. Valid data is
maintained at the output throughout the hidden refresh cycle. An internal address provides the refresh address
during hidden refresh.
CAS-before-RAS refresh
CAS-before-RAS (CBR) refresh is utilized by bringing CAS low earlier than RAS (see parameter t
CSR
) and
holding it low after RAS falls (see parameter t
CHR
). For successive CAS-before-RAS refresh cycles, CAS
remains low while cycling RAS. For this mode of refresh, the external addresses are ignored and the refresh
address is generated internally.
A low-power battery-backup refresh mode that requires less than 500
μ
A refresh current is available on the
TMS416100P. Data integrity is maintained using CAS-before-RAS refresh with a period of 62.5
μ
s while holding
RAS low for less than 1
μ
s. To minimize current consumption, all input levels need to be at CMOS levels
(V
IL
≤
0.2 V, V
IH
≤
V
CC
– 0.2 V).
power up
To achieve proper device operation, an initial pause of 200
μ
s followed by a minimum of eight initialization cycles
is required after full V
CC
level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
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PDF描述 |
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| TMS416100-60DZ | x1 Fast Page Mode DRAM |
| TMS416100-70DGA | x1 Fast Page Mode DRAM |
| TMS416100-70DJ | x1 Fast Page Mode DRAM |
| TMS416100-70DZ | x1 Fast Page Mode DRAM |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMS416100-60DZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
| TMS416100-70DGA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
| TMS416100-70DJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
| TMS416100-70DZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
| TMS416100-80DGA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
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