參數(shù)資料
型號(hào): TMS470R1B768PGEQR
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP144
封裝: PLASTIC, LQFP-144
文件頁(yè)數(shù): 35/49頁(yè)
文件大?。?/td> 552K
代理商: TMS470R1B768PGEQR
SCIn ISOSYNCHRONOUS MODE TIMINGS EXTERNAL CLOCK
Timing Requirements for External Clock SCIn Isosynchronous Mode
(1) (2)
Data Valid
SCICLK
SCITX
SCIRX
tc(SCC)
tw(SCCH)
tw(SCCL)
td(SCCH TXV)
tv(TX)
tsu(RX SCCL)
tv(SCCL RX)
SPNS108B – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
MIN
MAX
UNIT
tc(SCC)
Cycle time, SCInCLK(3)
8tc(ICLK)
ns
tw(SCCH)
Pulse duration, SCInCLK high
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
tw(SCCL)
Pulse duration, SCInCLK low
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
td(SCCH-TXV)
Delay time, SCInCLK high to SCInTX valid
2tc(ICLK) + 12 + tr
ns
tv(TX)
Valid time, SCInTX data after SCInCLK low
2tc(SCC) – 10
ns
tsu(RX-SCCL)
Setup time, SCInRX before SCInCLK low
0
ns
tv(SCCL-RX)
Valid time, SCInRX data after SCInCLK low
2tc(ICLK) + 10
ns
(1)
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
(2)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(3)
When driving an external SCInCLK, the following must be true: tc(SCC) ≥ 8tc(ICLK).
A.
Data transmission / reception characteristics for isosynchronous mode with external clocking are similar to the
asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK
falling edge.
Figure 17. SCIn Isosynchronous Mode Timing Diagram for External Clock
40
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1B768
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