參數(shù)資料
型號(hào): TMX320C6414TGLZ
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述: 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù): 114/140頁
文件大?。?/td> 2033K
代理商: TMX320C6414TGLZ
SPRS226H NOVEMBER 2003 REVISED AUGUST 2005
114
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415T AND C6416T ONLY]
timing requirements for PCLK
(see Figure 47)
NO.
600
720
850
1G
MIN
UNIT
MAX
1
tc(PCLK)
tw(PCLKH)
tw(PCLKL)
tsr(PCLK)
Cycle time, PCLK
30 (or 8P§)
ns
2
Pulse duration, PCLK high
11
ns
3
Pulse duration, PCLK low
v/
t slew rate, PCLK
11
ns
4
1
4
V/ns
For 3.3-V operation, the reference points for the rise and fall transitions are measured at VILP MAX and VIHP MIN.
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
§Select the parameter value of 30 ns or 8P, whichever is greater.
PCLK
1
2
3
4
4
0.4 DVDD V MIN
Peak to Peak for
3.3V signaling
Figure 47. PCLK Timing
timing requirements for PCI reset (see Figure 48)
NO.
600
720
850
1G
UNIT
MIN
MAX
1
tw(PRST)
tsu(PCLKA-PRSTH)
Pulse duration, PRST
1
ms
μ
s
2
Setup time, PCLK active before PRST high
100
PRST
PCLK
2
1
Figure 48. PCI Reset (PRST) Timing
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