SPRS457E
– MARCH 2009 – REVISED JUNE 2011
6.17 Multi-Channel Buffered Serial Port (McBSP)
The primary use for the Multi-Channel Buffered Serial Port (McBSP) is for audio interface purposes. The
primary audio modes that are supported by the McBSP are the AC97 and IIS modes. In addition to the
primary audio modes, the McBSP supports general serial port receive and transmit operation, but is not
intended to be used as a high-speed interface. The McBSP supports the following features:
Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
Direct interface to AC97 compliant devices (the necessary multiphase frame synchronization capability
is provided)
Direct interface to IIS compliant devices
Direct interface to SPI protocol in master mode only
A wide selection of data sizes, including 8, 12, 16, 20, 24, and 32 bits
μ-Law and A-Law companding
8-bit data transfers with the option of LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
Highly programmable internal clock and frame generation
Direct interface to T1/E1 Framers
Multi-channel transmit and receive of up to 128 channels
For more detailed information on the McBSP peripheral, see the Documentation Support section for the
Multi-Channel Buffered Serial Port (McBSP) Reference Guide.
6.17.1 McBSP Peripheral Register Description(s)
Table 6-72 lists the McBSP registers, their corresponding acronyms, and the device memory locations
(offsets).
Table 6-72. McBSP Registers
Offset
Acronym
Register Name
-
RBR(1)
Receive buffer register
-
RSR(1)
Receive shift register
-
XSR(1)
Transmit shift register
00h
DRR(2) (3)
Data receive register
04h
DXR(3)
Data transmit register
08h
SPCR
Serial port control register
0Ch
RCR
Receive control register
10h
XCR
Transmit control register
14h
SRGR
Sample rate generator register
18h
MCR
Multichannel Control Register
Enhanced Receive Channel Enable Register
1Ch
RCERE0
0 Partition A/B
(1)
The RBR, RSR, and XSR are not directly accessible via the CPUs or the EDMA controller.
(2)
The CPUs and EDMA controller can only read this register; they cannot write to it.
(3)
The DRR and DXR are accessible via the CPUs or the EDMA controller.
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Peripheral Information and Electrical Specifications
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2009–2011, Texas Instruments Incorporated