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| 型號(hào)： | TMX320DM648ZUT720 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Digital Media Processor |
| 中文描述： | 數(shù)字媒體處理器 |
| 文件頁(yè)數(shù)： | 94/166頁(yè) |
| 文件大?。?/td> | 1341K |
| 代理商： | TMX320DM648ZUT720 |
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6.9 DDR2 Memory Controller
6.9.1
DDR2 Memory Controller Device-Specific Information
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
The 32-bit DDR2 memory controller bus of the DM647/DM648 is used to interface to JESD79D-2A
standard-compliant DDR2 SDRAM devices. The DDR2 external bus interfaces only to DDR2 SDRAM
devices; it does not share the bus with any other types of peripherals. The decoupling of DDR2 memories
from other devices both simplifies board design and provides I/O concurrency from a second external
memory interface, EMIFA.
The internal data bus clock frequency and DDR2 bus clock frequency directly affect the maximum
throughput of the DDR2 bus. The data rate of the DDR2 bus is equal to the CLKIN2 frequency multiplied
by 20. The internal data bus clock frequency of the DDR2 memory controller is fixed at a divide-by-three
ratio of the CPU frequency. The maximum DDR2 throughput is determined by the smaller of the two bus
frequencies. For example, if the internal data bus frequency is 300 MHz (CPU frequency is 900 MHz) and
the DDR2 data rate is 533 MHz (266 MHz clock rate as CLKIN2 frequency is 26.6 MHz), the maximum
data rate achievable by the DDR2 memory controller is 2.13 Gbytes/sec.
The approach to specifying interface timing for the DDR2 memory bus is different than on other interfaces
such as EMIF and HPI. For these other interfaces the device timing was specified in terms of data manual
specifications and I/O buffer information specification (IBIS) models.
For the DM647/DM648 DDR2 memory bus, the approach is to specify compatible DDR2 devices and
provide the printed circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI)
has performed the simulation and system characterization to be sure all DDR2 interface timings in this
solution are met. The complete DDR2 system solution is documented in the
Implementing DDR2 PCB
Layout on the TMS320DM647/DM648 DMSoC
(literature number SPRAAK9) and TI supports only designs
that follow the guidelines in this application report.
The DDR2 Memory Controller pins must be enabled by setting the DDR2_EN configuration pin (ABA0)
high during device reset.
The ODT[1:0] pins of the memory controller must be left unconnected. The ODT pins on the DDR2
memory device(s) must be connected to ground.
The DDR2 memory controller on the DM647/DM648 devices supports the following memory topologies:
A 32-bit wide configuration interfacing to two 16-bit wide DDR2 SDRAM devices.
A 16-bit wide configuration interfacing to a single 16-bit wide DDR2 SDRAM device.
A race condition may exist when certain masters write data to the DDR2 memory controller. For example,
if master A passes a software message via a buffer in external memory and does not wait for indication
that the write completes, when master B attempts to read the software message, then the master B read
may bypass the master A write and, thus, master B may read stale data and, therefore, receive an
incorrect message.
Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete
before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have
hardware specification of write-read ordering, it may be necessary to specify data ordering via software.
If master A does not wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write.
2. Perform a dummy write to the DDR2 memory controller module ID and revision register.
3. Perform a dummy read to the DDR2 memory controller module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The
completion of the read in step 3 ensures that the previous write was done.
The master peripherals that need to implement this workaround are HPI, PCI, and VLYNQ.
Peripheral Information and Electrical Specifications
94
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMX320DM648ZUT9 | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Dig Media Processor RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMX320DM648ZUT900 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Media Processor |
| TMX320DM648ZUTQ7 | 制造商:Texas Instruments 功能描述: |
| TMX320DM8147BCYE0 | 制造商:Texas Instruments 功能描述: |
| TMX320DM8147BCYE2 | 制造商:Texas Instruments 功能描述: |
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