參數(shù)資料
型號(hào)： TP3056BDW
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
中文描述： 整體式串行接口的PCM編解碼器和過(guò)濾器
文件頁(yè)數(shù)： 15/19頁(yè)
文件大小： 287K
代理商： TP3056BDW
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCMCODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
short-frame sync operation
The device can operate with either a short-frame sync pulse or a long-frame sync pulse. On power up, the device
automatically goes into the short-frame mode where both FSX and FSR must be one bit-clock period long with
timing relationships specified in Figure 1. With FSX high during a falling edge of BCLK, the next rising edge of
BCLK enables the 3-state output buffer, outputting the sign bit at DX. The remaining seven bits are shifted out
on the following seven rising edges, with the next falling edge disabling DX. With FSR high during a falling edge
of BCLK, the next falling edge of BCLK latches in the sign bit. The following seven falling edges latch in the seven
remaining bits.
long-frame sync operation
Both FSX and FSR must be three or more bit-clock periods long to use the long-frame sync mode with timing
relationships as shown in Figure 2. Using the transmit frame sync (FSX), the device determines whether a short-
or long-frame sync pulse is being used. For 64-kHz operation, the frame-sync pulse must be kept low for a
minimum of 160 ns. The rising edge of FSX or BCLK, whichever occurs later, enables the 3-state output buffer,
outputting the sign bit at DX. The next seven rising edges of BCLK shift out the remaining seven bits. The falling
edge of BCLK following the eighth rising edge, or FSX going low, whichever occurs later, disables DX. A
rising edge on FSR, the receive-frame sync pulse, causes the PCM data at DR to be latched in on the next eight
falling edges of BCLK.
transmit section
The transmit section consists of an input amplifier, filters, and an encoding ADC. The input is an operational
amplifier with provision for gain adjustment using two external resistors. The low-noise and wide-bandwidth
characteristics of these devices provide gains in excess of 20 dB across the audio passband. The operational
amplifier drives a unity-gain filter consisting of an RC active prefilter followed by an eighth-order
switched-capacitor band-pass filter clocked at 256 kHz. The output of this filter is routed to the encoder
sample-and-hold circuit. The ADC is a compressing type and converts the analog signal to PCM data in
accordance with
μ
-law or A-law coding conventions, as selected. A precision voltage reference provides a
nominal input overload voltage of 2.5 V peak.
The sampling of the filter output is controlled by the FSX frame-sync pulse; then the successive-approximation
encoding cycle begins. The resulting 8-bit code is loaded into a buffer and shifted out through DX at the next
FSX pulse. The total encoding delay is approximately 290
μ
s. Any offset voltage due to the filters or comparator
is cancelled by sign-bit integration.
receive section
The receive section is unity gain and consists of an expanding DAC, filters, and a power amplifier. Decoding
is
μ
-law or A-law (as selected by the ASEL terminal), and the decoded analog output signal is routed to the input
of a fifth-order switched-capacitor low-pass filter. This filter is clocked at 256 kHz and corrects for the (sin x)/x
attenuation caused by the 8-kHz sample/hold of the DAC. Next is a second-order RC active post-filter/power
amplifier capable of driving an external 600-
load.
When FSR goes high, the data at DR is stepped in on the falling edge of the next eight BCLK clocks. At the
end of the decoder time slot, the decoding cycle begins and 10
μ
s later, the decoder DAC output is updated.
The decoder delay is about 10
μ
s (decoder update) plus 110
μ
s (filter delay) plus 62.5
μ
s (1/2 frame), or a total
of approximately 180
μ
s.
相關(guān)PDF資料
PDF描述
TP3056BN MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
TP3098 TRANSISTOR | BJT | NPN | 200MA I(C) | RFMOD
TP3102 1 Cell Li-ion Battery Protection + Cell Pack
TP3330N MODEM
TP3330V MODEM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TP3056BDWR 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TP3056BN 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TP3056J 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PARALLEL INTERFACE CODEC/FILTER COMBO
TP3056V 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law CODEC
TP3057 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Enhanced Serial Interface CODEC/Filter COMBO Family
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*