參數(shù)資料
型號: TP3056BDW
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
中文描述: 整體式串行接口的PCM編解碼器和過濾器
文件頁數(shù): 5/19頁
文件大小: 287K
代理商: TP3056BDW
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCMCODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics at V
CC
= 5 V
±
5%, V
BB
= –5 V
±
5%, GND at 0 V, T
A
= 25
°
C (unless
otherwise noted)
digital interface
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VOH
High-level output voltage
DX
IH = -3.2 mA
IL = 3.2 mA
IL = 3.2 mA,
VI = VIH to VCC
VI = GND to VIL
VO = GND to VCC
2.4
V
VOL
Low level output voltage
Low-level output voltage
DX
0.4
V
TSX
Drain open
0.4
±
10
±
10
±
10
IIH
IIL
IOZ
High-level input current
μ
A
μ
A
μ
A
Low-level input current
All digital inputs
Output current in high-impedance state
DX
analog interface with transmit amplifier input
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±
2.5
±
200
UNIT
VICR
II
ri
AV
BI
VIO
CMRR
Common-mode input voltage range
V
Input current
VFXI+ or VFXI –
VI = –2.5 V to 2.5 V
VI = –2.5 V to 2.5 V
nA
M
Input resistance
VFXI+ or VFXI –
10
Open-loop voltage amplification
VFXI+ to GSX
5000
Unity-gain bandwidth
GSX
1
2
MHz
Input offset voltage
VFXI+ or VFXI –
±
20
mV
Common-mode rejection ratio
60
dB
KSVR
All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25
°
C.
Measured with CMRR > 60 dB.
Supply-voltage rejection ratio
60
dB
analog interface with receive amplifier output
PARAMETER
TEST CONDITIONS
RL = 10 k
MIN
TYP
MAX
±
2.5
UNIT
Receive output drive voltage
V
pF
Output resistance
VFRO
1
3
Load resistance
VFRO =
±
2.5 V
600
Load capacitance
VFRO to GND
500
±
200
Output dc offset voltage
All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25
°
C.
VFRO to GND
mV
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