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參數(shù)資料
| 型號： | TP3064WM-X |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE ENHANCED SER 20SOIC |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 類型： | PCM 編解碼器/濾波器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 8 b |
| ADC / DAC 數(shù)量： | 1 / 1 |
| 三角積分調(diào)變： | 無 |
| 電壓 - 電源，模擬： | ±5V |
| 電壓 - 電源，數(shù)字： | ±5V |
| 工作溫度： | -25°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | *TP3064WM-X |
Connection Diagrams
Dual-In-Line Package
TLH5070 – 2
Top View
Plastic Chip Carrier
TLH5070 – 6
Top View
Order Number TP3064J or TP3067J
See NS Package J20A
Order Number TP3064WM or TP3067WM
See NS Package M20B
Order Number TP3064N or TP3067N
See NS Package N20A
Order Number TP3064V or TP3067V
See NS Package V20A
Pin Description
Symbol
Function
VPOa
The non-inverted output of the receive power
amplifier
GNDA
Analog ground All signals are referenced to
this pin
VPOb
The inverted output of the receive power
amplifier
VPI
Inverting input to the receive power amplifier
VFRO
Analog output of the receive filter
VCC
Positive power supply pin VCCea5Vg5%
FSR
Receive frame sync pulse which enables
BCLKR to shift PCM data into DR FSR is an
8 kHz pulse train See
Figures 2 and 3 for
timing details
DR
Receive data input PCM data is shifted into
DR following the FSR leading edge
BCLKR
The bit clock which shifts data into DR after
the FSR leading edge May vary from 64 kHz
CLKSEL
to 2048 MHz Alternatively may be a logic
input which selects either
1536 MHz1544 MHz or 2048 MHz for
master clock in synchronous mode and
BCLKX is used for both transmit and receive
directions (see Table I)
MCLKR
Receive master clock Must be 1536 MHz
1544 MHz or 2048 MHz May be
PDN
asynchronous with MCLKX but should be
synchronous with MCLKX for best
performance When MCLKR is connected
continuously low MCLKX is selected for all
internal timing When MCLKR is connected
continuously high the device is powered
down
Symbol
Function
MCLKX
Transmit master clock Must be 1536 MHz
1544 MHz or 2048 MHz May be
asynchronous with MCLKR Best
performance is realized from synchronous
operation
BCLKX
The bit clock which shifts out the PCM data
on DX May vary from 64 kHz to 2048 MHz
but must be synchronous with MCLKX
DX
The TRI-STATE PCM data output which is
enabled by FSX
FSX
Transmit frame sync pulse input which
enables BCLKX to shift out the PCM data on
DX FSX is an 8 kHz pulse train see Figures 2
and
3 for timing details
TSX
Open drain output which pulses low during
the encoder time slot
ANLB
Analog Loopback control input Must be set
to logic ‘0’ for normal operation When pulled
to logic ‘1’ the transmit filter input is
disconnected from the output of the transmit
preamplifier and connected to the VPOa
output of the receive power amplifier
GSX
Analog output of the transmit input amplifier
Used to externally set gain
VFXIb
Inverting input of the transmit input amplifier
VFXIa
Non-inverting input of the transmit input
amplifier
VBB
Negative power supply pin VBBeb5Vg5%
2
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| TP3067AN | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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