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參數(shù)資料
| 型號(hào)： | TP3064WM-X |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE ENHANCED SER 20SOIC |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 類型： | PCM 編解碼器/濾波器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 8 b |
| ADC / DAC 數(shù)量： | 1 / 1 |
| 三角積分調(diào)變： | 無 |
| 電壓 - 電源，模擬： | ±5V |
| 電壓 - 電源，數(shù)字： | ±5V |
| 工作溫度： | -25°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | *TP3064WM-X |
Functional Description
POWER-UP
When power is first applied power-on reset circuitry initializ-
es the COMBOTM and places it into a power-down state All
non-essential circuits are deactivated and the DX VFRO
VPOb and VPOa outputs are put in high impedance states
To power-up the device a logical low level or clock must be
applied to the MCLKR PDN pin and FSX andor FSR pulses
must be present Thus 2 power-down control modes are
available The first is to pull the MCLKR PDN pin high the
alternative is to hold both FSX and FSR inputs continuously
lowthe device will power-down approximately 2 ms after
the last FSX or FSR pulse Power-up will occur on the first
FSX or FSR pulse The TRI-STATE PCM data output DX
will remain in the high impedance state until the second FSX
pulse
SYNCHRONOUS OPERATION
For synchronous operation the same master clock and bit
clock should be used for both the transmit and receive di-
rections In this mode a clock must be applied to MCLKX
and the MCLKR PDN pin can be used as a power-down
control A low level on MCLKR PDN powers up the device
and a high level powers down the device In either case
MCLKX will be selected as the master clock for both the
transmit and receive circuits A bit clock must also be ap-
plied to BCLKX and the BCLKR CLKSEL can be used to
select the proper internal divider for a master clock of 1536
MHz 1544 MHz or 2048 MHz For 1544 MHz operation
the device automatically compensates for the 193rd clock
pulse each frame
With a fixed level on the BCLKR CLKSEL pin BLCKX will be
selected as the bit clock for both the transmit and receive
directions Table I indicates the frequencies of operation
which can be selected depending on the state of BCLKR
CLKSEL In this synchronous mode the bit clock BCLKX
may be from 64 kHz to 2048 MHz but must be synchro-
nous with MCLKX
Each FSX pulse begins the encoding cycle and the PCM
data from the previous encode cycle is shifted out of the
enabled DX output on the positive edge of BCLKX After 8
bit clock periods the TRI-STATE DX output is returned to a
high impedance state With an FSR pulse PCM data is
latched via the DR input on the negative edge of BCLKX (or
BCLKR if running) FSX and FSR must be synchronous with
MCLKXR
TABLE I Selection of Master Clock Frequencies
Master Clock
BCLKR CLKSEL
Frequency Selected
TP3067
TP3064
Clocked
2048 MHz
1536 MHz or
1544 MHz
0
1536 MHz or
2048 MHz
1544 MHz
1
2048 MHz
1536 MHz or
1544 MHz
ASYNCHRONOUS OPERATION
For asynchronous operation separate transmit and receive
clocks may be applied MCLKX and MCLKR must be 2048
MHz for the TP3067 or 1536 MHZ 1544 MHz for the
TP3064 and need not be synchronous For best transmis-
sion performance however MCLKR should be synchronous
with MCLKX which is easily achieved by applying only static
logic levels to the MCLKR PDN pin This will automatically
connect MCLKX to all internal MCLKR functions (see Pin
Description) For 1544 MHz operation the device automati-
cally compensates for the 193rd clock pulse each frame
FSX starts each encoding cycle and must be synchronous
with MCLKX and BCLKX FSR starts each decoding cycle
and must be synchronous with BCLKR BCLKR must be a
clock the logic levels shown in Table I are not valid in asyn-
chronous mode BCLKX and BCLKR may operate from 64
kHz to 2048 MHz
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse (the
same as the TP302021 CODECs) or a long frame sync
pulse Upon power initialization the device assumes a short
frame mode In this mode both frame sync pulses FSX and
FSR must be one bit clock period long with timing relation-
ships specified in
Figure 2 With FSX high during a falling
edge of BCLKX the next rising edge of BCLKX enables the
DX TRI-STATE output buffer which will output the sign bit
The following seven rising edges clock out the remaining
seven bits and the next falling edge disables the DX output
With FSR high during a falling edge of BCLKR (BCLKX in
synchronous mode) the next falling edge of BCLKR latches
in the sign bit The following seven falling edges latch in the
seven remaining bits All devices may utilize the short frame
sync pulse in synchronous or asynchronous operating
mode
LONG FRAME SYNC OPERATION
To use the long (TP5116A56 CODECs) frame mode both
the frame sync pulses FSX and FSR must be three or more
bit clock periods long with timing relationships specified in
Figure 3 Based on the transmit frame sync FSX the COM-
BO will sense whether short or long frame sync pulses are
being used For 64 kHz operation the frame sync pulse
must be kept low for a minimum of 160 ns The DX TRI-
STATE output buffer is enabled with the rising edge of FSX
or the rising edge of BCLKX whichever comes later and the
first bit clocked out is the sign bit The following seven
BCLKX rising edges clock out the remaining seven bits The
DX output is disabled by the falling BCLKX edge following
the eighth rising edge or by FSX going low whichever
comes later A rising edge on the receive frame sync pulse
FSR will cause the PCM data at DR to be latched in on the
next eight falling edges of BCLKR(BCLKX in synchronous
mode) All devices may utilize the long frame sync pulse in
synchronous or asynchronous mode
TRANSMIT SECTION
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors
see
Figure 4 The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be real-
ized The op amp drives a unity-gain filter consisting of RC
active pre-filter followed by an eighth order switched-ca-
pacitor bandpass filter clocked at 256 kHz The output of
this filter directly drives the encoder sample-and-hold circuit
The AD is of companding type according to m-law
(TP3064) or A-law (TP3067) coding conventions A preci-
sion voltage reference is trimmed in manufacturing to pro-
vide an input overload (tMAX) of nominally 25V peak (see
3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3067 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:``Enhanced' Serial Interface CMOS CODEC/Filter COMBO |
| TP3067A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3067ADW | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP3067AJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law CODEC |
| TP3067AN | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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